0 X86 : NOP L: [no true dep.] T: 0.00ns= 0.000c 1 X86 : 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 2 X86 : 2x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 3 X86 : 3x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 4 X86 : 4x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 5 X86 : 5x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 6 X86 : 6x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 7 X86 : 7x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 8 X86 : 8x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 9 X86 : 9x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 10 X86 : 10x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 11 X86 : 11x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 12 X86 : 12x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 13 X86 : 13x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 14 X86 : 14x 0x66 NOP L: [no true dep.] T: 0.00ns= 0.000c 15 SSE2 : PAUSE L: [no true dep.] T: 0.00ns= 0.000c 16 X86 :{REX} MOV r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 17 X86 :{REX} MOV r16, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 18 X86 :{REX} MOV r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 19 AMD64 :{REX} MOV r64, imm64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 20 X86 :{REX} MOV r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 21 X86 :{REX} MOV r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 22 X86 :{REX} MOV r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 23 AMD64 :{REX} MOV r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 24 X86 :{REX} MOV r8, [m8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 25 X86 :{REX} MOV r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 26 X86 :{REX} MOV r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 27 AMD64 :{REX} MOV r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 28 X86 :{REX} MOV [m8], r8 L: [memory dep.] T: 0.00ns= 0.000c 29 X86 :{REX} MOV [m16], r16 L: [memory dep.] T: 0.00ns= 0.000c 30 X86 :{REX} MOV [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 31 X86 :{REX} MOV [m32 + 2], r32 L: [memory dep.] T: 0.00ns= 0.000c 32 AMD64 :{REX} MOV [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 33 AMD64 :{REX} MOV [m64 + 4], r64 L: [memory dep.] T: 0.00ns= 0.000c 34 X86 :{REX} MOV r8,[m8]+MOV [m8],r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 35 X86 :{REX} MOV r16,[m16]+MOV [m16],r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 36 X86 :{REX} MOV r32,[m32]+MOV [m32],r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 37 AMD64 :{REX} MOV r64,[m64]+MOV [m64],r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 38 SSE2 :{REX} MOVNTI [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 39 AMD64 :{REX} MOVNTI [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 40 CMOV :{REX} CMOVNZ r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 41 CMOV :{REX} CMOVNZ r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 42 AMD64 :{REX} CMOVNZ r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 43 X86 :{REX} MOVSX r16, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 44 X86 :{REX} MOVSX r32, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 45 AMD64 :{REX} MOVSX r64, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 46 X86 :{REX} MOVSX r32, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 47 AMD64 :{REX} MOVSX r64, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 48 AMD64 :{REX} MOVSXD r64, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 49 X86 :{REX} MOVZX r16, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 50 X86 :{REX} MOVZX r32, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 51 AMD64 :{REX} MOVZX r64, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 52 X86 :{REX} MOVZX r32, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 53 AMD64 :{REX} MOVZX r64, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 54 X86 :{REX} XCHG r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 55 X86 :{REX} XCHG r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 56 X86 :{REX} XCHG r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 57 AMD64 :{REX} XCHG r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 58 X86 :{REX} XCHG r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 59 X86 :{REX} XCHG r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 60 X86 :{REX} XCHG r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 61 AMD64 :{REX} XCHG r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 62 X86 :{REX} XCHG r8, [m8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 63 X86 :{REX} XCHG r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 64 X86 :{REX} XCHG r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 65 AMD64 :{REX} XCHG r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 66 X86 :{REX} ADD r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 67 X86 :{REX} ADD r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 68 X86 :{REX} ADD r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 69 AMD64 :{REX} ADD r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 70 X86 :{REX} ADD r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 71 X86 :{REX} ADD r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 72 X86 :{REX} ADD r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 73 AMD64 :{REX} ADD r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 74 X86 :{REX} ADD r8, [m8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 75 X86 :{REX} ADD r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 76 X86 :{REX} ADD r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 77 AMD64 :{REX} ADD r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 78 X86 :{REX} ADD [m8], r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 79 X86 :{REX} ADD [m16], r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 80 X86 :{REX} ADD [m32], r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 81 X86 :{REX} ADD [m32 + 2], r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 82 AMD64 :{REX} ADD [m64], r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 83 AMD64 :{REX} ADD [m64 + 4], r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 84 X86 :{REX} LOCK ADD [m8], r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 85 X86 :{REX} LOCK ADD [m16], r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 86 X86 :{REX} LOCK ADD [m32], r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 87 X86 :{REX} LOCK ADD [m32 + 2], r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 88 AMD64 :{REX} LOCK ADD [m64], r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 89 AMD64 :{REX} LOCK ADD [m64 + 4], r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 90 X86 :{REX} ADD r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 91 X86 :{REX} ADD r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 92 X86 :{REX} ADD r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 93 AMD64 :{REX} ADD r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 94 X86 :{REX} ADD r16, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 95 X86 :{REX} ADD r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 96 AMD64 :{REX} ADD r64, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 97 X86 :{REX} ADD [m8], imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 98 X86 :{REX} ADD [m16], imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 99 X86 :{REX} ADD [m32], imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 100 AMD64 :{REX} ADD [m64], imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 101 X86 :{REX} ADD [m16], imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 102 X86 :{REX} ADD [m32], imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 103 AMD64 :{REX} ADD [m64], imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 104 X86 :{REX} ADD al, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 105 X86 :{REX} ADD ax, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 106 X86 :{REX} ADD eax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 107 AMD64 :{REX} ADD rax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 108 X86 :{REX} SUB r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 109 X86 :{REX} SUB r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 110 X86 :{REX} SUB r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 111 AMD64 :{REX} SUB r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 112 X86 :{REX} SUB r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 113 X86 :{REX} SUB r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 114 X86 :{REX} SUB r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 115 AMD64 :{REX} SUB r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 116 X86 :{REX} ADC r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 117 X86 :{REX} ADC r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 118 X86 :{REX} ADC r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 119 AMD64 :{REX} ADC r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 120 X86 :{REX} SBB r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 121 X86 :{REX} SBB r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 122 X86 :{REX} SBB r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 123 AMD64 :{REX} SBB r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 124 X86 :{REX} SBB r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 125 X86 :{REX} SBB r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 126 X86 :{REX} SBB r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 127 AMD64 :{REX} SBB r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 128 X86 :{REX} CMP r8, r8 L: [no true dep.] T: 0.00ns= 0.000c 129 X86 :{REX} CMP r16, r16 L: [no true dep.] T: 0.00ns= 0.000c 130 X86 :{REX} CMP r32, r32 L: [no true dep.] T: 0.00ns= 0.000c 131 AMD64 :{REX} CMP r64, r64 L: [no true dep.] T: 0.00ns= 0.000c 132 X86 :{REX} CMP r1_8, r2_8 L: [no true dep.] T: 0.00ns= 0.000c 133 X86 :{REX} CMP r1_16, r2_16 L: [no true dep.] T: 0.00ns= 0.000c 134 X86 :{REX} CMP r1_32, r2_32 L: [no true dep.] T: 0.00ns= 0.000c 135 AMD64 :{REX} CMP r1_64, r2_64 L: [no true dep.] T: 0.00ns= 0.000c 136 X86 :{REX} AND r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 137 X86 :{REX} AND r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 138 X86 :{REX} AND r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 139 AMD64 :{REX} AND r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 140 X86 :{REX} AND r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 141 X86 :{REX} AND r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 142 X86 :{REX} AND r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 143 AMD64 :{REX} AND r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 144 X86 :{REX} OR r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 145 X86 :{REX} OR r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 146 X86 :{REX} OR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 147 AMD64 :{REX} OR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 148 X86 :{REX} OR r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 149 X86 :{REX} OR r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 150 X86 :{REX} OR r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 151 AMD64 :{REX} OR r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 152 X86 :{REX} XOR r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 153 X86 :{REX} XOR r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 154 X86 :{REX} XOR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 155 AMD64 :{REX} XOR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 156 X86 :{REX} XOR r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 157 X86 :{REX} XOR r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 158 X86 :{REX} XOR r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 159 AMD64 :{REX} XOR r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 160 X86 :{REX} NEG r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 161 X86 :{REX} NEG r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 162 X86 :{REX} NEG r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 163 AMD64 :{REX} NEG r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 164 X86 :{REX} NOT r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 165 X86 :{REX} NOT r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 166 X86 :{REX} NOT r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 167 AMD64 :{REX} NOT r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 168 X86 :{REX} TEST r8, r8 L: [no true dep.] T: 0.00ns= 0.000c 169 X86 :{REX} TEST r16, r16 L: [no true dep.] T: 0.00ns= 0.000c 170 X86 :{REX} TEST r32, r32 L: [no true dep.] T: 0.00ns= 0.000c 171 AMD64 :{REX} TEST r64, r64 L: [no true dep.] T: 0.00ns= 0.000c 172 X86 :{REX} TEST r1_8, r2_8 L: [no true dep.] T: 0.00ns= 0.000c 173 X86 :{REX} TEST r1_16, r2_16 L: [no true dep.] T: 0.00ns= 0.000c 174 X86 :{REX} TEST r1_32, r2_32 L: [no true dep.] T: 0.00ns= 0.000c 175 AMD64 :{REX} TEST r1_64, r2_64 L: [no true dep.] T: 0.00ns= 0.000c 176 X86 :{REX} BT r16, r16 L: [no true dep.] T: 0.00ns= 0.000c 177 X86 :{REX} BT r32, r32 L: [no true dep.] T: 0.00ns= 0.000c 178 AMD64 :{REX} BT r64, r64 L: [no true dep.] T: 0.00ns= 0.000c 179 X86 :{REX} BT r16, imm8 L: [no true dep.] T: 0.00ns= 0.000c 180 X86 :{REX} BT r32, imm8 L: [no true dep.] T: 0.00ns= 0.000c 181 AMD64 :{REX} BT r64, imm8 L: [no true dep.] T: 0.00ns= 0.000c 182 X86 :{REX} BTC r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 183 X86 :{REX} BTC r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 184 AMD64 :{REX} BTC r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 185 X86 :{REX} BTC r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 186 X86 :{REX} BTC r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 187 AMD64 :{REX} BTC r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 188 X86 :{REX} BTR r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 189 X86 :{REX} BTR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 190 AMD64 :{REX} BTR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 191 X86 :{REX} BTR r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 192 X86 :{REX} BTR r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 193 AMD64 :{REX} BTR r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 194 X86 :{REX} BTS r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 195 X86 :{REX} BTS r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 196 AMD64 :{REX} BTS r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 197 X86 :{REX} BTS r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 198 X86 :{REX} BTS r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 199 AMD64 :{REX} BTS r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 200 X86 :{REX} SETC r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 201 X86 :{REX} INC r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 202 X86 :{REX} INC r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 203 X86 :{REX} INC r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 204 AMD64 :{REX} INC r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 205 AMD64 :{REX} LEA r16, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 206 AMD64 :{REX} LEA r32, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 207 AMD64 :{REX} LEA r64, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 208 AMD64 :{REX} LEA r16, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 209 AMD64 :{REX} LEA r32, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 210 AMD64 :{REX} LEA r64, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 211 AMD64 :{REX} LEA r16, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 212 AMD64 :{REX} LEA r32, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 213 AMD64 :{REX} LEA r64, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 214 AMD64 :{REX} LEA r16, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 215 AMD64 :{REX} LEA r32, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 216 AMD64 :{REX} LEA r64, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 217 X86 :{REX} SHL r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 218 X86 :{REX} SHL r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 219 X86 :{REX} SHL r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 220 AMD64 :{REX} SHL r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 221 X86 :{REX} SHL r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 222 X86 :{REX} SHL r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 223 X86 :{REX} SHL r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 224 AMD64 :{REX} SHL r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 225 X86 :{REX} SHL r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 226 X86 :{REX} SHL r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 227 X86 :{REX} SHL r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 228 AMD64 :{REX} SHL r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 229 X86 :{REX} SHR r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 230 X86 :{REX} SHR r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 231 X86 :{REX} SHR r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 232 AMD64 :{REX} SHR r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 233 X86 :{REX} SHR r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 234 X86 :{REX} SHR r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 235 X86 :{REX} SHR r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 236 AMD64 :{REX} SHR r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 237 X86 :{REX} SHR r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 238 X86 :{REX} SHR r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 239 X86 :{REX} SHR r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 240 AMD64 :{REX} SHR r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 241 X86 :{REX} SAR r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 242 X86 :{REX} SAR r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 243 X86 :{REX} SAR r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 244 AMD64 :{REX} SAR r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 245 X86 :{REX} SAR r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 246 X86 :{REX} SAR r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 247 X86 :{REX} SAR r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 248 AMD64 :{REX} SAR r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 249 X86 :{REX} SAR r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 250 X86 :{REX} SAR r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 251 X86 :{REX} SAR r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 252 AMD64 :{REX} SAR r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 253 X86 :{REX} SHLD r1_16, r1_16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 254 X86 :{REX} SHLD r1_32, r1_32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 255 AMD64 :{REX} SHLD r1_64, r1_64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 256 X86 :{REX} SHLD r1_16, r1_16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 257 X86 :{REX} SHLD r1_32, r1_32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 258 AMD64 :{REX} SHLD r1_64, r1_64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 259 X86 :{REX} SHRD r1_16, r1_16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 260 X86 :{REX} SHRD r1_32, r1_32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 261 AMD64 :{REX} SHRD r1_64, r1_64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 262 X86 :{REX} SHRD r1_16, r1_16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 263 X86 :{REX} SHRD r1_32, r1_32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 264 AMD64 :{REX} SHRD r1_64, r1_64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 265 X86 :{REX} ROL r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 266 X86 :{REX} ROL r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 267 X86 :{REX} ROL r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 268 AMD64 :{REX} ROL r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 269 X86 :{REX} ROL r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 270 X86 :{REX} ROL r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 271 X86 :{REX} ROL r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 272 AMD64 :{REX} ROL r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 273 X86 :{REX} ROL r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 274 X86 :{REX} ROL r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 275 X86 :{REX} ROL r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 276 AMD64 :{REX} ROL r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 277 X86 :{REX} ROR r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 278 X86 :{REX} ROR r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 279 X86 :{REX} ROR r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 280 AMD64 :{REX} ROR r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 281 X86 :{REX} ROR r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 282 X86 :{REX} ROR r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 283 X86 :{REX} ROR r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 284 AMD64 :{REX} ROR r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 285 X86 :{REX} ROR r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 286 X86 :{REX} ROR r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 287 X86 :{REX} ROR r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 288 AMD64 :{REX} ROR r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 289 X86 :{REX} RCL r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 290 X86 :{REX} RCL r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 291 X86 :{REX} RCL r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 292 AMD64 :{REX} RCL r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 293 X86 :{REX} RCL r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 294 X86 :{REX} RCL r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 295 X86 :{REX} RCL r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 296 AMD64 :{REX} RCL r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 297 X86 :{REX} RCL r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 298 X86 :{REX} RCL r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 299 X86 :{REX} RCL r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 300 AMD64 :{REX} RCL r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 301 X86 :{REX} RCR r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 302 X86 :{REX} RCR r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 303 X86 :{REX} RCR r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 304 AMD64 :{REX} RCR r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 305 X86 :{REX} RCR r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 306 X86 :{REX} RCR r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 307 X86 :{REX} RCR r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 308 AMD64 :{REX} RCR r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 309 X86 :{REX} RCR r8, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 310 X86 :{REX} RCR r16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 311 X86 :{REX} RCR r32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 312 AMD64 :{REX} RCR r64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 313 X86 :{REX} BSF r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 314 X86 :{REX} BSF r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 315 AMD64 :{REX} BSF r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 316 X86 :{REX} BSR r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 317 X86 :{REX} BSR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 318 AMD64 :{REX} BSR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 319 X86 :{REX} BSWAP r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 320 AMD64 :{REX} BSWAP r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 321 MOVBE :{REX} MOVBE r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 322 MOVBE :{REX} MOVBE r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 323 MOVBE_X64 :{REX} MOVBE r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 324 MOVBE :{REX} MOVBE [m16], r16 L: [memory dep.] T: 0.00ns= 0.000c 325 MOVBE :{REX} MOVBE [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 326 MOVBE_X64 :{REX} MOVBE [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 327 X86 :{REX} IMUL r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 328 X86 :{REX} IMUL r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 329 AMD64 :{REX} IMUL r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 330 X86 :{REX} IMUL r16, r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 331 X86 :{REX} IMUL r32, r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 332 AMD64 :{REX} IMUL r64, r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 333 X86 :{REX} IMUL r16, r16, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 334 X86 :{REX} IMUL r32, r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 335 AMD64 :{REX} IMUL r64, r64, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 336 X86 :{REX} IMUL r8l al/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 337 X86 :{REX} IMUL r16 ax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 338 X86 :{REX} IMUL r32 eax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 339 AMD64 :{REX} IMUL r64 rax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 340 X86 :{REX} MUL r8l al/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 341 X86 :{REX} MUL r16 ax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 342 X86 :{REX} MUL r32 eax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 343 AMD64 :{REX} MUL r64 rax/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 344 X86 :{REX} IMUL r8l ah/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 345 X86 :{REX} IMUL r16 dx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 346 X86 :{REX} IMUL r32 edx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 347 AMD64 :{REX} IMUL r64 rdx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 348 X86 :{REX} MUL r8l ah/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 349 X86 :{REX} MUL r16 dx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 350 X86 :{REX} MUL r32 edx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 351 AMD64 :{REX} MUL r64 rdx/eax upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 352 X86 :{REX} IDIV r8l 14/ 7b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 353 X86 :{REX} IDIV r8l 12/ 6b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 354 X86 :{REX} IDIV r8l 7/ 7b L: [no true dep.] T: 0.00ns= 0.000c 355 X86 :{REX} IDIV r8l 4/ 7b L: [no true dep.] T: 0.00ns= 0.000c 356 X86 :{REX} IDIV r8l 0/ 7b L: [no true dep.] T: 0.00ns= 0.000c 357 X86 :{REX} IDIV r8l 11/ 4b L: [no true dep.] T: 0.00ns= 0.000c 358 X86 :{REX} IDIV r8l 8/ 4b L: [no true dep.] T: 0.00ns= 0.000c 359 X86 :{REX} IDIV r8l 4/ 4b L: [no true dep.] T: 0.00ns= 0.000c 360 X86 :{REX} IDIV r8l 0/ 4b L: [no true dep.] T: 0.00ns= 0.000c 361 X86 :{REX} IDIV r8l 2^12 /2^6 L: [no true dep.] T: 0.00ns= 0.000c 362 X86 :{REX} IDIV r8l 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 363 X86 :{REX} IDIV r8l 1/ 1 EAX upd L: [no true dep.] T: 0.00ns= 0.000c 364 X86 :{REX} IDIV r16 30/15b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 365 X86 :{REX} IDIV r16 26/13b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 366 X86 :{REX} IDIV r16 15/15b L: [no true dep.] T: 0.00ns= 0.000c 367 X86 :{REX} IDIV r16 8/15b L: [no true dep.] T: 0.00ns= 0.000c 368 X86 :{REX} IDIV r16 0/15b L: [no true dep.] T: 0.00ns= 0.000c 369 X86 :{REX} IDIV r16 23/ 8b L: [no true dep.] T: 0.00ns= 0.000c 370 X86 :{REX} IDIV r16 16/ 8b L: [no true dep.] T: 0.00ns= 0.000c 371 X86 :{REX} IDIV r16 8/ 8b L: [no true dep.] T: 0.00ns= 0.000c 372 X86 :{REX} IDIV r16 0/ 8b L: [no true dep.] T: 0.00ns= 0.000c 373 X86 :{REX} IDIV r16 2^28 /2^14 L: [no true dep.] T: 0.00ns= 0.000c 374 X86 :{REX} IDIV r16 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 375 X86 :{REX} IDIV r16 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 376 X86 :{REX} IDIV r16 1/ 1 rDX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 377 X86 :{REX} IDIV r32 62/31b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 378 X86 :{REX} IDIV r32 56/28b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 379 X86 :{REX} IDIV r32 48/31b L: [no true dep.] T: 0.00ns= 0.000c 380 X86 :{REX} IDIV r32 31/31b L: [no true dep.] T: 0.00ns= 0.000c 381 X86 :{REX} IDIV r32 16/31b L: [no true dep.] T: 0.00ns= 0.000c 382 X86 :{REX} IDIV r32 0/31b L: [no true dep.] T: 0.00ns= 0.000c 383 X86 :{REX} IDIV r32 47/16b L: [no true dep.] T: 0.00ns= 0.000c 384 X86 :{REX} IDIV r32 32/16b L: [no true dep.] T: 0.00ns= 0.000c 385 X86 :{REX} IDIV r32 16/16b L: [no true dep.] T: 0.00ns= 0.000c 386 X86 :{REX} IDIV r32 0/16b L: [no true dep.] T: 0.00ns= 0.000c 387 X86 :{REX} IDIV r32 2^60 /2^30 L: [no true dep.] T: 0.00ns= 0.000c 388 X86 :{REX} IDIV r32 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 389 X86 :{REX} IDIV r32 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 390 X86 :{REX} IDIV r32 1/ 1 rDX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 391 AMD64 :{REX} IDIV r64 126/63b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 392 AMD64 :{REX} IDIV r64 126/63b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 393 AMD64 :{REX} IDIV r64 96/63b L: [no true dep.] T: 0.00ns= 0.000c 394 AMD64 :{REX} IDIV r64 63/63b L: [no true dep.] T: 0.00ns= 0.000c 395 AMD64 :{REX} IDIV r64 32/63b L: [no true dep.] T: 0.00ns= 0.000c 396 AMD64 :{REX} IDIV r64 0/63b L: [no true dep.] T: 0.00ns= 0.000c 397 AMD64 :{REX} IDIV r64 95/32b L: [no true dep.] T: 0.00ns= 0.000c 398 AMD64 :{REX} IDIV r64 64/32b L: [no true dep.] T: 0.00ns= 0.000c 399 AMD64 :{REX} IDIV r64 32/32b L: [no true dep.] T: 0.00ns= 0.000c 400 AMD64 :{REX} IDIV r64 0/32b L: [no true dep.] T: 0.00ns= 0.000c 401 AMD64 :{REX} IDIV r64 2^124/2^62 L: [no true dep.] T: 0.00ns= 0.000c 402 AMD64 :{REX} IDIV r64 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 403 AMD64 :{REX} IDIV r64 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 404 AMD64 :{REX} IDIV r64 1/ 1 rDX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 405 X86 :{REX} DIV r8l 16/ 8b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 406 X86 :{REX} DIV r8l 12/ 8b L: [no true dep.] T: 0.00ns= 0.000c 407 X86 :{REX} DIV r8l 8/ 8b L: [no true dep.] T: 0.00ns= 0.000c 408 X86 :{REX} DIV r8l 4/ 8b L: [no true dep.] T: 0.00ns= 0.000c 409 X86 :{REX} DIV r8l 0/ 8b L: [no true dep.] T: 0.00ns= 0.000c 410 X86 :{REX} DIV r8l 12/ 4b L: [no true dep.] T: 0.00ns= 0.000c 411 X86 :{REX} DIV r8l 8/ 4b L: [no true dep.] T: 0.00ns= 0.000c 412 X86 :{REX} DIV r8l 4/ 4b L: [no true dep.] T: 0.00ns= 0.000c 413 X86 :{REX} DIV r8l 0/ 4b L: [no true dep.] T: 0.00ns= 0.000c 414 X86 :{REX} DIV r8l 2^14 /2^7 L: [no true dep.] T: 0.00ns= 0.000c 415 X86 :{REX} DIV r8l 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 416 X86 :{REX} DIV r8l 1/ 1 EAX upd L: [no true dep.] T: 0.00ns= 0.000c 417 X86 :{REX} DIV r16 32/16b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 418 X86 :{REX} DIV r16 30/15b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 419 X86 :{REX} DIV r16 24/16b L: [no true dep.] T: 0.00ns= 0.000c 420 X86 :{REX} DIV r16 16/16b L: [no true dep.] T: 0.00ns= 0.000c 421 X86 :{REX} DIV r16 8/16b L: [no true dep.] T: 0.00ns= 0.000c 422 X86 :{REX} DIV r16 0/16b L: [no true dep.] T: 0.00ns= 0.000c 423 X86 :{REX} DIV r16 24/ 8b L: [no true dep.] T: 0.00ns= 0.000c 424 X86 :{REX} DIV r16 16/ 8b L: [no true dep.] T: 0.00ns= 0.000c 425 X86 :{REX} DIV r16 8/ 8b L: [no true dep.] T: 0.00ns= 0.000c 426 X86 :{REX} DIV r16 0/ 8b L: [no true dep.] T: 0.00ns= 0.000c 427 X86 :{REX} DIV r16 2^30 /2^15 L: [no true dep.] T: 0.00ns= 0.000c 428 X86 :{REX} DIV r16 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 429 X86 :{REX} DIV r16 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 430 X86 :{REX} DIV r32 64/32b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 431 X86 :{REX} DIV r32 62/31b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 432 X86 :{REX} DIV r32 48/32b L: [no true dep.] T: 0.00ns= 0.000c 433 X86 :{REX} DIV r32 32/32b L: [no true dep.] T: 0.00ns= 0.000c 434 X86 :{REX} DIV r32 16/32b L: [no true dep.] T: 0.00ns= 0.000c 435 X86 :{REX} DIV r32 0/32b L: [no true dep.] T: 0.00ns= 0.000c 436 X86 :{REX} DIV r32 48/16b L: [no true dep.] T: 0.00ns= 0.000c 437 X86 :{REX} DIV r32 32/16b L: [no true dep.] T: 0.00ns= 0.000c 438 X86 :{REX} DIV r32 16/16b L: [no true dep.] T: 0.00ns= 0.000c 439 X86 :{REX} DIV r32 0/16b L: [no true dep.] T: 0.00ns= 0.000c 440 X86 :{REX} DIV r32 2^62 /2^31 L: [no true dep.] T: 0.00ns= 0.000c 441 X86 :{REX} DIV r32 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 442 X86 :{REX} DIV r32 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 443 X86 :{REX} DIV r32 1/ 1 rDX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 444 AMD64 :{REX} DIV r64 128/64b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 445 AMD64 :{REX} DIV r64 126/63b L: 0.00ns= 0.00c T: 0.00ns= 0.000c 446 AMD64 :{REX} DIV r64 96/64b L: [no true dep.] T: 0.00ns= 0.000c 447 AMD64 :{REX} DIV r64 64/64b L: [no true dep.] T: 0.00ns= 0.000c 448 AMD64 :{REX} DIV r64 32/64b L: [no true dep.] T: 0.00ns= 0.000c 449 AMD64 :{REX} DIV r64 0/64b L: [no true dep.] T: 0.00ns= 0.000c 450 AMD64 :{REX} DIV r64 96/32b L: [no true dep.] T: 0.00ns= 0.000c 451 AMD64 :{REX} DIV r64 64/32b L: [no true dep.] T: 0.00ns= 0.000c 452 AMD64 :{REX} DIV r64 32/32b L: [no true dep.] T: 0.00ns= 0.000c 453 AMD64 :{REX} DIV r64 0/32b L: [no true dep.] T: 0.00ns= 0.000c 454 AMD64 :{REX} DIV r64 2^126/2^63 L: [no true dep.] T: 0.00ns= 0.000c 455 AMD64 :{REX} DIV r64 1/ 1 no upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 456 AMD64 :{REX} DIV r64 1/ 1 rAX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 457 AMD64 :{REX} DIV r64 1/ 1 rDX upd L: 0.00ns= 0.00c T: 0.00ns= 0.000c 458 X86 : CBW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 459 X86 : CWDE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 460 AMD64 : CDQE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 461 X86 : CWD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 462 X86 : CDQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 463 AMD64 : CQO L: 0.00ns= 0.00c T: 0.00ns= 0.000c 464 X86 : CLC L: 0.00ns= 0.00c T: 0.00ns= 0.000c 465 X86 : STC L: 0.00ns= 0.00c T: 0.00ns= 0.000c 466 X86 : CMC L: 0.00ns= 0.00c T: 0.00ns= 0.000c 467 X86 : CLD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 468 X86 : STD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 469 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 470 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 471 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 472 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 473 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 474 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 475 LAHF : LAHF L: 0.00ns= 0.00c T: 0.00ns= 0.000c 476 LAHF : SAHF L: 0.00ns= 0.00c T: 0.00ns= 0.000c 477 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 478 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 479 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 480 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 481 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 482 DefISA :DefInst L: 0.00ns= 0.00c T: 0.00ns= 0.000c 483 X86 :{REX} PUSH r16 L: [no true dep.] T: 0.00ns= 0.000c 484 X86 :{REX} POP r16 L: [no true dep.] T: 0.00ns= 0.000c 485 X86 :{REX} PUSH r16 + POP r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 486 AMD64 :{REX} PUSH r64 L: [no true dep.] T: 0.00ns= 0.000c 487 AMD64 :{REX} POP r64 L: [no true dep.] T: 0.00ns= 0.000c 488 AMD64 :{REX} PUSH r64 + POP r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 489 AMD64 :{REX} PUSH imm8 L: [no true dep.] T: 0.00ns= 0.000c 490 AMD64 :{REX} PUSH imm8 + POP r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 491 AMD64 :{REX} PUSH imm32 L: [no true dep.] T: 0.00ns= 0.000c 492 AMD64 :{REX} PUSH imm32 + POP r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 493 X86 :{REX} PUSH [m16] L: [no true dep.] T: 0.00ns= 0.000c 494 X86 :{REX} POP [m16] L: [no true dep.] T: 0.00ns= 0.000c 495 X86 :{REX} PUSH [m16] + POP [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 496 AMD64 :{REX} PUSH [m64] L: [no true dep.] T: 0.00ns= 0.000c 497 AMD64 :{REX} POP [m64] L: [no true dep.] T: 0.00ns= 0.000c 498 AMD64 :{REX} PUSH [m64] + POP [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 499 X86 : PUSHF L: [no true dep.] T: 0.00ns= 0.000c 500 DefISA :DefInst L: [no true dep.] T: 0.00ns= 0.000c 501 X86 : PUSHF + POPF L: 0.00ns= 0.00c T: 0.00ns= 0.000c 502 AMD64 : PUSHFQ L: [no true dep.] T: 0.00ns= 0.000c 503 DefISA :DefInst L: [no true dep.] T: 0.00ns= 0.000c 504 AMD64 : PUSHFQ + POPFQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 505 X86 : CMPSB L: 0.00ns= 0.00c T: 0.00ns= 0.000c 506 X86 : CMPSW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 507 X86 : CMPSD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 508 AMD64 : CMPSQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 509 X86 : REPE CMPSB DefStrRes 510 X86 : REPE CMPSW DefStrRes 511 X86 : REPE CMPSD DefStrRes 512 AMD64 : REPE CMPSQ DefStrRes 513 X86 : LODSB L: 0.00ns= 0.00c T: 0.00ns= 0.000c 514 X86 : LODSW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 515 X86 : LODSD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 516 AMD64 : LODSQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 517 X86 : REP LODSB DefStrRes 518 X86 : REP LODSW DefStrRes 519 X86 : REP LODSD DefStrRes 520 AMD64 : REP LODSQ DefStrRes 521 X86 : STOSB L: 0.00ns= 0.00c T: 0.00ns= 0.000c 522 X86 : STOSW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 523 X86 : STOSD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 524 AMD64 : STOSQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 525 X86 : REP STOSB DefStrRes 526 X86 : REP STOSW DefStrRes 527 X86 : REP STOSD DefStrRes 528 AMD64 : REP STOSQ DefStrRes 529 X86 : MOVSB L: 0.00ns= 0.00c T: 0.00ns= 0.000c 530 X86 : MOVSW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 531 X86 : MOVSD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 532 AMD64 : MOVSQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 533 X86 : REP MOVSB DefStrRes 534 X86 : REP MOVSW DefStrRes 535 X86 : REP MOVSD DefStrRes 536 AMD64 : REP MOVSQ DefStrRes 537 X86 : SCASB L: 0.00ns= 0.00c T: 0.00ns= 0.000c 538 X86 : SCASW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 539 X86 : SCASD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 540 AMD64 : SCASQ L: 0.00ns= 0.00c T: 0.00ns= 0.000c 541 X86 : REPNE SCASB DefStrRes 542 X86 : REPNE SCASW DefStrRes 543 X86 : REPNE SCASD DefStrRes 544 AMD64 : REPNE SCASQ DefStrRes 545 X86 :{REX} XADD r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 546 X86 :{REX} XADD r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 547 X86 :{REX} XADD r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 548 AMD64 :{REX} XADD r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 549 X86 :{REX} CMPXCHG r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 550 X86 :{REX} CMPXCHG r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 551 X86 :{REX} CMPXCHG r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 552 AMD64 :{REX} CMPXCHG r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 553 CMPX8 :{REX} CMPXCHG8B [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 554 CMPX16 :{REX} CMPXCHG16B [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 555 X86 : RDTSC L: [no true dep.] T: 0.00ns= 0.000c 556 X86 : CPUID (EAX = 0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 557 X86 : CPUID (EAX = 1) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 558 POPCNT :{REX} POPCNT r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 559 POPCNT :{REX} POPCNT r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 560 POPCNT_X64 :{REX} POPCNT r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 561 ABM :{REX} LZCNT r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 562 ABM :{REX} LZCNT r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 563 ABM_X64 :{REX} LZCNT r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 564 SSE4.2 :{REX} CRC32 r32, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 565 SSE4.2 :{REX} CRC32 r32, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 566 SSE4.2 :{REX} CRC32 r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 567 SSE42_X64 :{REX} CRC32 r64, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 568 SSE42_X64 :{REX} CRC32 r64, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 569 X87 : FNOP L: [no true dep.] T: 0.00ns= 0.000c 570 X87 : FXCH st(i) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 571 X87 : FCHS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 572 X87 : FABS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 573 X87 : FTST L: [no true dep.] T: 0.00ns= 0.000c 574 X87 : FXAM L: [no true dep.] T: 0.00ns= 0.000c 575 CMOV : FCMOVE st, st(i) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 576 X87 : FADD st(i), st (st = 0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 577 X87 : FADD st(i), st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 578 X87 : FADD st, st(i), FXCH st(i) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 579 X87 : FMUL st(i), st (st = 0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 580 X87 : FMUL st(i), st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 581 X87 : FMUL st, st(i), FXCH st(i) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 582 X87 : FMUL + FADD st, st(i) L: 0.00ns= 0.00c T: [not enough reg] 583 X87 : FMUL st(2i) FADD st(2i+1) L: 0.00ns= 0.00c T: [not enough reg] 584 X87 : FDIV32 st(i), st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 585 X87 : FDIV64 st(i), st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 586 X87 : FDIV80 st(i), st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 587 X87 : FDIV80 (0.0l/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 588 X87 : FDIV80 (x/1.0l) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 589 X87 : FDIV80 (x/2.0l) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 590 X87 : FDIV80 (x/0.5l) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 591 X87 : FSQRT32 st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 592 X87 : FSQRT64 st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 593 X87 : FSQRT80 st L: 0.00ns= 0.00c T: 0.00ns= 0.000c 594 X87 : FSQRT80 (0.0l) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 595 X87 : FSQRT80 (1.0l) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 596 X87 : FDECSTP L: [no true dep.] T: 0.00ns= 0.000c 597 X87 : FINCSTP L: [no true dep.] T: 0.00ns= 0.000c 598 X87 : FCOM st(i) L: [no true dep.] T: 0.00ns= 0.000c 599 CMOV : FCOMI st, st(i) L: [no true dep.] T: 0.00ns= 0.000c 600 X87 : FSIN80 (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 601 X87 : FSIN80 (0.0) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 602 X87 : FSIN80 (1.0) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 603 X87 : FSIN80 (4Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 604 X87 : FSIN80 (2Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 605 X87 : FSIN80 (Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 606 X87 : FSIN80 (Pi/2) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 607 X87 : FSIN80 (Pi/4) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 608 X87 : FSIN80 (Pi/8) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 609 X87 : FSIN80 (Pi/16) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 610 X87 : FSIN80 (Pi/32) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 611 X87 : FCOS80 (0.73908513...) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 612 X87 : FCOS80 (0.73908513...)+FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 613 X87 : FCOS80 (0.0) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 614 X87 : FCOS80 (1.0) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 615 X87 : FCOS80 (4Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 616 X87 : FCOS80 (2Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 617 X87 : FCOS80 (Pi) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 618 X87 : FCOS80 (Pi/2) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 619 X87 : FCOS80 (Pi/4) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 620 X87 : FCOS80 (Pi/8) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 621 X87 : FCOS80 (Pi/16) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 622 X87 : FCOS80 (Pi/32) + FADD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 623 MMX : EMMS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 624 MMX :{REX} MOVD r32, mm L: [diff. reg. set] T: 0.00ns= 0.000c 625 MMX :{REX} MOVD mm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 626 MMX :{REX} MOVD r32, mm+MOVD mm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 627 AMD64 :{REX} MOVD r64, mm L: [diff. reg. set] T: 0.00ns= 0.000c 628 AMD64 :{REX} MOVD mm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 629 AMD64 :{REX} MOVD r64, mm+MOVD mm, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 630 MMX :{REX} MOVD mm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 631 MMX :{REX} MOVD [m32], mm L: [memory dep.] T: 0.00ns= 0.000c 632 MMX :{REX} MOVD mm,[m32]+MOVD [m32],mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 633 MMX :{REX} MOVQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 634 MMX :{REX} MOVQ mm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 635 MMX :{REX} MOVQ [m64], mm L: [memory dep.] T: 0.00ns= 0.000c 636 MMX :{REX} MOVQ mm,[m64]+MOVQ [m64],mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 637 SSE :{REX} MOVNTQ [m64], mm L: [memory dep.] T: 0.00ns= 0.000c 638 SSE :{REX} PMOVMSKB r32, mm L: [diff. reg. set] T: 0.00ns= 0.000c 639 AMD64 :{REX} PMOVMSKB r64, mm L: [diff. reg. set] T: 0.00ns= 0.000c 640 SSE : MASKMOVQ mm, mm L: [memory dep.] T: 0.00ns= 0.000c 641 MMX : PADDB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 642 MMX : PADDW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 643 MMX : PADDD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 644 SSE2 : PADDQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 645 MMX : PADDSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 646 MMX : PADDSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 647 MMX : PADDUSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 648 MMX : PADDUSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 649 MMX : PSUBB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 650 MMX : PSUBB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 651 MMX : PSUBW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 652 MMX : PSUBW mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 653 MMX : PSUBD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 654 MMX : PSUBD mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 655 SSE2 : PSUBQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 656 SSE2 : PSUBQ mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 657 MMX : PSUBSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 658 MMX : PSUBSB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 659 MMX : PSUBSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 660 MMX : PSUBSW mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 661 MMX : PSUBUSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 662 MMX : PSUBUSB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 663 MMX : PSUBUSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 664 MMX : PSUBUSW mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 665 MMX : PCMPEQB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 666 MMX : PCMPEQB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 667 MMX : PCMPEQW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 668 MMX : PCMPEQW mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 669 MMX : PCMPEQD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 670 MMX : PCMPEQD mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 671 MMX : PCMPGTB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 672 MMX : PCMPGTB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 673 MMX : PCMPGTW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 674 MMX : PCMPGTW mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 675 MMX : PCMPGTD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 676 MMX : PCMPGTD mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 677 MMX : PAND mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 678 MMX : PAND mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 679 MMX : PANDN mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 680 MMX : PANDN mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 681 MMX : POR mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 682 MMX : POR mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 683 MMX : PXOR mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 684 MMX : PXOR mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 685 MMX : PMULHW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 686 SSE : PMULHUW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 687 3DNOW : PMULHRW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 688 SSSE3 : PMULHRSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 689 MMX : PMULLW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 690 SSE2 : PMULUDQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 691 SSSE3 : PMADDUBSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 692 MMX : PMADDWD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 693 MMX : PSLLW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 694 MMX : PSLLW mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 695 MMX : PSLLD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 696 MMX : PSLLD mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 697 MMX : PSLLQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 698 MMX : PSLLQ mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 699 MMX : PSRAW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 700 MMX : PSRAW mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 701 MMX : PSRAD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 702 MMX : PSRAD mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 703 MMX : PSRLW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 704 MMX : PSRLW mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 705 MMX : PSRLD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 706 MMX : PSRLD mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 707 MMX : PSRLQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 708 MMX : PSRLQ mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 709 MMX : PUNPCKHBW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 710 MMX : PUNPCKHWD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 711 MMX : PUNPCKHDQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 712 MMX : PUNPCKLBW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 713 MMX : PUNPCKLWD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 714 MMX : PUNPCKLDQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 715 MMX : PACKSSWB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 716 MMX : PACKUSWB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 717 MMX : PACKSSDW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 718 3DNOW : FEMMS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 719 3DNOW : PFSUB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 720 3DNOW : PFSUB mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 721 3DNOW : PFSUBR mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 722 3DNOW : PFSUBR mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 723 3DNOW : PFADD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 724 3DNOW : PFMUL mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 725 3DNOW : PFADD+PFMUL mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 726 3DNOW : PFADD m1, m1 PFMUL m2, m2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 727 3DNOW : PFACC mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 728 3DNOW : PFCMPEQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 729 3DNOW : PFCMPEQ mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 730 3DNOW : PFCMPGE mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 731 3DNOW : PFCMPGE mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 732 3DNOW : PFCMPGT mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 733 3DNOW : PFCMPGT mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 734 3DNOW : PFRCP mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 735 3DNOW : PFRCPIT1 mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 736 3DNOW : PFRCPIT2 mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 737 3DNOW : PFRSQIT1 mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 738 3DNOW : PFRSQRT mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 739 3DNOW : PFMAX mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 740 3DNOW : PFMIN mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 741 3DNOW : PF2ID mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 742 3DNOW : PI2FD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 743 3DNOW : PF2ID mm, mm + PI2FD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 744 3DNOW : PAVGUSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 745 3DNOW : PREFETCH [mem] L: [memory dep.] T: 0.00ns= 0.000c 746 3DN_3DNPREF :{REX} PREFETCHW [mem] L: [memory dep.] T: 0.00ns= 0.000c 747 3DNOWP : PFNACC mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 748 3DNOWP : PFPNACC mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 749 3DNOWP : PSWAPD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 750 3DNOWP : PF2IW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 751 3DNOWP : PI2FW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 752 3DNOWP : PF2IW mm, mm + PI2FW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 753 SSE : PAVGB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 754 SSE : PAVGW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 755 SSE :{REX} PEXTRW r32, mm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 756 SSE :{REX} PINSRW mm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 757 SSE :{REX} PEXTRW + PINSRW r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 758 AMD64 :{REX} PEXTRW r64, mm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 759 AMD64 :{REX} PINSRW mm, r64, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 760 AMD64 :{REX} PEXTRW + PINSRW r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 761 SSE : PMAXSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 762 SSE : PMAXUB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 763 SSE : PMINSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 764 SSE : PMINUB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 765 SSE : PSADBW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 766 SSE : PSHUFW mm, mm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 767 SSE :{REX} PREFETCHNTA [mem] L: [memory dep.] T: 0.00ns= 0.000c 768 SSE :{REX} PREFETCHT0 [mem] L: [memory dep.] T: 0.00ns= 0.000c 769 SSE :{REX} PREFETCHT1 [mem] L: [memory dep.] T: 0.00ns= 0.000c 770 SSE :{REX} PREFETCHT2 [mem] L: [memory dep.] T: 0.00ns= 0.000c 771 SSE : SFENCE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 772 SSE2 : LFENCE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 773 SSE2 : MFENCE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 774 SSSE3 : PABSB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 775 SSSE3 : PABSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 776 SSSE3 : PABSD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 777 SSSE3 : PALIGNR mm, mm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 778 SSSE3 : PHADDW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 779 SSSE3 : PHADDD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 780 SSSE3 : PHADDSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 781 SSSE3 : PHSUBW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 782 SSSE3 : PHSUBD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 783 SSSE3 : PHSUBSW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 784 SSSE3 : PSHUFB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 785 SSSE3 : PSIGNB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 786 SSSE3 : PSIGNW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 787 SSSE3 : PSIGND mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 788 SSE :{REX} MOVHLPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 789 SSE :{REX} MOVHLPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 790 AVX :{VEX} VMOVHLPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 791 AVX :{VEX} VMOVHLPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 792 SSE :{REX} MOVSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 793 AVX :{VEX} VMOVSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 794 SSE :{REX} MOVSS xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 795 SSE :{REX} MOVSS [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 796 SSE :{REX} MOVSS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 797 AVX :{VEX} VMOVSS xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 798 AVX :{VEX} VMOVSS [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 799 AVX :{VEX} VMOVSS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 800 SSE :{REX} MOVLPS xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 801 SSE :{REX} MOVLPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 802 SSE :{REX} MOVLPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 803 AVX :{VEX} VMOVLPS xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 804 AVX :{VEX} VMOVLPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 805 AVX :{VEX} VMOVLPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 806 SSE :{REX} MOVHPS xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 807 SSE :{REX} MOVHPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 808 SSE :{REX} MOVHPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 809 AVX :{VEX} VMOVHPS xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 810 AVX :{VEX} VMOVHPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 811 AVX :{VEX} VMOVHPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 812 SSE :{REX} MOVAPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 813 SSE :{REX} MOVAPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 814 SSE :{REX} MOVAPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 815 SSE :{REX} MOVAPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 816 AVX :{VEX} VMOVAPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 817 AVX :{VEX} VMOVAPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 818 AVX :{VEX} VMOVAPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 819 AVX :{VEX} VMOVAPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 820 SSE :{REX} MOVUPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 821 SSE :{REX} MOVUPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 822 SSE :{REX} MOVUPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 823 SSE :{REX} MOVUPS aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 824 SSE :{REX} MOVUPS xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 825 SSE :{REX} MOVUPS [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 826 SSE :{REX} MOVUPS unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 827 AVX :{VEX} VMOVUPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 828 AVX :{VEX} VMOVUPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 829 AVX :{VEX} VMOVUPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 830 AVX :{VEX} VMOVUPS aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 831 AVX :{VEX} VMOVUPS xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 832 AVX :{VEX} VMOVUPS [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 833 AVX :{VEX} VMOVUPS unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 834 SSE4A :{REX} MOVNTSS [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 835 SSE :{REX} MOVNTPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 836 AVX :{VEX} VMOVNTPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 837 SSE :{REX} MOVMSKPS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 838 AVX :{VEX} VMOVMSKPS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 839 AVX :{VEX} VMASKMOVPS xmm,xmm,[m128+4] L: [memory dep.] T: 0.00ns= 0.000c 840 AVX :{VEX} VMASKMOVPS [m128+4],xmm,xmm L: [memory dep.] T: 0.00ns= 0.000c 841 AVX :{VEX} VMASKMOVPS unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 842 SSE :{REX} UNPCKLPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 843 AVX :{VEX} VUNPCKLPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 844 SSE :{REX} UNPCKHPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 845 AVX :{VEX} VUNPCKHPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 846 SSE :{REX} SHUFPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 847 AVX :{VEX} VSHUFPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 848 AVX :{VEX} VPERMILPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 849 AVX :{VEX} VPERMILPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 850 SSE :{REX} COMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 851 AVX :{VEX} VCOMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 852 SSE :{REX} UCOMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 853 AVX :{VEX} VUCOMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 854 SSE :{REX} CMPSS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 855 SSE :{REX} CMPPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 856 AVX :{VEX} VCMPSS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 857 AVX :{VEX} VCMPPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 858 SSE :{REX} SUBSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 859 AVX :{VEX} VSUBSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 860 SSE :{REX} SUBPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 861 AVX :{VEX} VSUBPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 862 SSE :{REX} ADDSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 863 AVX :{VEX} VADDSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 864 SSE :{REX} ADDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 865 AVX :{VEX} VADDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 866 SSE :{REX} MULSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 867 AVX :{VEX} VMULSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 868 SSE :{REX} MULPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 869 AVX :{VEX} VMULPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 870 SSE :{REX} MULSS+ADDSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 871 AVX :{VEX} VMULSS+VADDSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 872 SSE :{REX} MULPS+ADDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 873 AVX :{VEX} VMULPS+VADDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 874 SSE :{REX} MULSS xm1,xm1 ADDSS xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 875 AVX :{VEX} VMULSS xmm1.. VADDSS xmm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 876 SSE :{REX} MULPS xm1,xm1 ADDPS xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 877 AVX :{VEX} VMULPS xmm1.. VADDPS xmm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 878 SSE :{REX} MAXSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 879 AVX :{VEX} VMAXSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 880 SSE :{REX} MAXPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 881 AVX :{VEX} VMAXPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 882 SSE :{REX} MINSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 883 AVX :{VEX} VMINSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 884 SSE :{REX} MINPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 885 AVX :{VEX} VMINPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 886 SSE :{REX} ANDNPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 887 SSE :{REX} ANDNPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 888 AVX :{VEX} VANDNPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 889 AVX :{VEX} VANDNPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 890 SSE :{REX} ANDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 891 SSE :{REX} ANDPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 892 AVX :{VEX} VANDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 893 AVX :{VEX} VANDPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 894 SSE :{REX} ORPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 895 SSE :{REX} ORPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 896 AVX :{VEX} VORPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 897 AVX :{VEX} VORPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 898 SSE :{REX} XORPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 899 SSE :{REX} XORPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 900 AVX :{VEX} VXORPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 901 AVX :{VEX} VXORPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 902 SSE :{REX} DIVSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 903 SSE :{REX} DIVSS (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 904 SSE :{REX} DIVSS (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 905 SSE :{REX} DIVSS (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 906 SSE :{REX} DIVSS (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 907 AVX :{VEX} VDIVSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 908 AVX :{VEX} VDIVSS (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 909 AVX :{VEX} VDIVSS (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 910 AVX :{VEX} VDIVSS (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 911 AVX :{VEX} VDIVSS (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 912 SSE :{REX} DIVPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 913 SSE :{REX} DIVPS (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 914 SSE :{REX} DIVPS (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 915 SSE :{REX} DIVPS (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 916 SSE :{REX} DIVPS (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 917 AVX :{VEX} VDIVPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 918 AVX :{VEX} VDIVPS (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 919 AVX :{VEX} VDIVPS (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 920 AVX :{VEX} VDIVPS (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 921 AVX :{VEX} VDIVPS (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 922 SSE :{REX} SQRTSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 923 SSE :{REX} SQRTSS (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 924 SSE :{REX} SQRTSS (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 925 AVX :{VEX} VSQRTSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 926 AVX :{VEX} VSQRTSS (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 927 AVX :{VEX} VSQRTSS (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 928 SSE :{REX} SQRTPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 929 SSE :{REX} SQRTPS (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 930 SSE :{REX} SQRTPS (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 931 AVX :{VEX} VSQRTPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 932 AVX :{VEX} VSQRTPS (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 933 AVX :{VEX} VSQRTPS (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 934 SSE :{REX} RCPSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 935 AVX :{VEX} VRCPSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 936 SSE :{REX} RCPPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 937 AVX :{VEX} VRCPPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 938 SSE :{REX} RSQRTSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 939 AVX :{VEX} VRSQRTSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 940 SSE :{REX} RSQRTPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 941 AVX :{VEX} VRSQRTPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 942 SSE :{REX} CVTPI2PS xmm, mm L: [diff. reg. set] T: 0.00ns= 0.000c 943 SSE :{REX} CVTPS2PI mm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 944 SSE :{REX} CVTPS2PI + CVTPI2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 945 SSE :{REX} CVTTPS2PI mm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 946 SSE :{REX} CVTTPS2PI + CVTPI2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 947 SSE :{REX} CVTSI2SS xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 948 SSE :{REX} CVTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 949 SSE :{REX} CVTSS2SI + CVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 950 SSE :{REX} CVTTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 951 SSE :{REX} CVTTSS2SI + CVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 952 AVX :{VEX} VCVTSI2SS xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 953 AVX :{VEX} VCVTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 954 AVX :{VEX} VCVTSS2SI + VCVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 955 AVX :{VEX} VCVTTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 956 AVX :{VEX} VCVTTSS2SI + VCVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 957 AMD64 :{REX} CVTSI2SS xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 958 AMD64 :{REX} CVTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 959 AMD64 :{REX} CVTSS2SI + CVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 960 AMD64 :{REX} CVTTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 961 AMD64 :{REX} CVTTSS2SI + CVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 962 AVX_X64 :{VEX} VCVTSI2SS xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 963 AVX_X64 :{VEX} VCVTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 964 AVX_X64 :{VEX} VCVTSS2SI + VCVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 965 AVX_X64 :{VEX} VCVTTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 966 AVX_X64 :{VEX} VCVTTSS2SI + VCVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 967 SSE :{REX} STMXCSR [mem] L: [memory dep.] T: 0.00ns= 0.000c 968 SSE :{REX} LDMXCSR [mem] L: [memory dep.] T: 0.00ns= 0.000c 969 SSE :{REX} STMXCSR + LDMXCSR L: 0.00ns= 0.00c T: 0.00ns= 0.000c 970 SSE2 :{REX} MOVSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 971 SSE2 :{REX} MOVSD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 972 SSE2 :{REX} MOVSD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 973 SSE2 :{REX} MOVSD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 974 AVX :{VEX} VMOVSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 975 AVX :{VEX} VMOVSD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 976 AVX :{VEX} VMOVSD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 977 AVX :{VEX} VMOVSD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 978 SSE2 :{REX} MOVLPD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 979 SSE2 :{REX} MOVLPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 980 SSE2 :{REX} MOVLPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 981 AVX :{VEX} VMOVLPD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 982 AVX :{VEX} VMOVLPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 983 AVX :{VEX} VMOVLPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 984 SSE2 :{REX} MOVHPD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 985 SSE2 :{REX} MOVHPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 986 SSE2 :{REX} MOVHPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 987 AVX :{VEX} VMOVHPD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 988 AVX :{VEX} VMOVHPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 989 AVX :{VEX} VMOVHPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 990 SSE2 :{REX} MOVAPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 991 SSE2 :{REX} MOVAPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 992 SSE2 :{REX} MOVAPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 993 SSE2 :{REX} MOVAPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 994 AVX :{VEX} VMOVAPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 995 AVX :{VEX} VMOVAPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 996 AVX :{VEX} VMOVAPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 997 AVX :{VEX} VMOVAPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 998 SSE2 :{REX} MOVUPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 999 SSE2 :{REX} MOVUPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1000 SSE2 :{REX} MOVUPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1001 SSE2 :{REX} MOVUPD aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1002 SSE2 :{REX} MOVUPD xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1003 SSE2 :{REX} MOVUPD [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 1004 SSE2 :{REX} MOVUPD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1005 AVX :{VEX} VMOVUPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1006 AVX :{VEX} VMOVUPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1007 AVX :{VEX} VMOVUPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1008 AVX :{VEX} VMOVUPD aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1009 AVX :{VEX} VMOVUPD xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1010 AVX :{VEX} VMOVUPD [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 1011 AVX :{VEX} VMOVUPD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1012 SSE4A :{REX} MOVNTSD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 1013 SSE2 :{REX} MOVNTPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1014 AVX :{VEX} VMOVNTPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1015 SSE2 :{REX} MOVMSKPD r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1016 AVX :{VEX} VMOVMSKPD r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1017 AVX :{VEX} VMASKMOVPD xmm,xmm,[m128+4] L: [memory dep.] T: 0.00ns= 0.000c 1018 AVX :{VEX} VMASKMOVPD [m128+4],xmm,xmm L: [memory dep.] T: 0.00ns= 0.000c 1019 AVX :{VEX} VMASKMOVPD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1020 SSE2 :{REX} UNPCKLPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1021 AVX :{VEX} VUNPCKLPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1022 SSE2 :{REX} UNPCKHPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1023 AVX :{VEX} VUNPCKHPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1024 SSE2 :{REX} SHUFPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1025 AVX :{VEX} VSHUFPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1026 AVX :{VEX} VPERMILPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1027 AVX :{VEX} VPERMILPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1028 SSE2 :{REX} COMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1029 AVX :{VEX} VCOMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1030 SSE2 :{REX} UCOMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1031 AVX :{VEX} VUCOMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1032 SSE2 :{REX} CMPSD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1033 SSE2 :{REX} CMPPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1034 AVX :{VEX} VCMPSD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1035 AVX :{VEX} VCMPPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1036 SSE2 :{REX} SUBSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1037 AVX :{VEX} VSUBSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1038 SSE2 :{REX} SUBPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1039 AVX :{VEX} VSUBPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1040 SSE2 :{REX} ADDSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1041 AVX :{VEX} VADDSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1042 SSE2 :{REX} ADDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1043 AVX :{VEX} VADDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1044 SSE2 :{REX} MULSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1045 AVX :{VEX} VMULSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1046 SSE2 :{REX} MULPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1047 AVX :{VEX} VMULPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1048 SSE2 :{REX} MULSD+ADDSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1049 AVX :{VEX} VMULSD+VADDSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1050 SSE2 :{REX} MULPD+ADDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1051 AVX :{VEX} VMULPD+VADDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1052 SSE2 :{REX} MULSD xm1,xm1 ADDSD xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1053 AVX :{VEX} VMULSD xmm1.. VADDSD xmm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1054 SSE2 :{REX} MULPD xm1,xm1 ADDPD xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1055 AVX :{VEX} VMULPD xmm1.. VADDPD xmm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1056 SSE2 :{REX} MAXSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1057 AVX :{VEX} VMAXSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1058 SSE2 :{REX} MAXPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1059 AVX :{VEX} VMAXPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1060 SSE2 :{REX} MINSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1061 AVX :{VEX} VMINSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1062 SSE2 :{REX} MINPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1063 AVX :{VEX} VMINPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1064 SSE2 :{REX} ANDNPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1065 SSE2 :{REX} ANDNPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1066 AVX :{VEX} VANDNPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1067 AVX :{VEX} VANDNPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1068 SSE2 :{REX} ANDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1069 SSE2 :{REX} ANDPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1070 AVX :{VEX} VANDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1071 AVX :{VEX} VANDPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1072 SSE2 :{REX} ORPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1073 SSE2 :{REX} ORPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1074 AVX :{VEX} VORPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1075 AVX :{VEX} VORPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1076 SSE2 :{REX} XORPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1077 SSE2 :{REX} XORPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1078 AVX :{VEX} VXORPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1079 AVX :{VEX} VXORPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1080 SSE2 :{REX} DIVSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1081 SSE2 :{REX} DIVSD (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1082 SSE2 :{REX} DIVSD (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1083 SSE2 :{REX} DIVSD (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1084 SSE2 :{REX} DIVSD (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1085 AVX :{VEX} VDIVSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1086 AVX :{VEX} VDIVSD (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1087 AVX :{VEX} VDIVSD (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1088 AVX :{VEX} VDIVSD (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1089 AVX :{VEX} VDIVSD (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1090 SSE2 :{REX} DIVPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1091 SSE2 :{REX} DIVPD (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1092 SSE2 :{REX} DIVPD (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1093 SSE2 :{REX} DIVPD (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1094 SSE2 :{REX} DIVPD (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1095 AVX :{VEX} VDIVPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1096 AVX :{VEX} VDIVPD (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1097 AVX :{VEX} VDIVPD (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1098 AVX :{VEX} VDIVPD (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1099 AVX :{VEX} VDIVPD (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1100 SSE2 :{REX} SQRTSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1101 SSE2 :{REX} SQRTSD (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1102 SSE2 :{REX} SQRTSD (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1103 AVX :{VEX} VSQRTSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1104 AVX :{VEX} VSQRTSD (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1105 AVX :{VEX} VSQRTSD (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1106 SSE2 :{REX} SQRTPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1107 SSE2 :{REX} SQRTPD (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1108 SSE2 :{REX} SQRTPD (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1109 AVX :{VEX} VSQRTPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1110 AVX :{VEX} VSQRTPD (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1111 AVX :{VEX} VSQRTPD (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1112 SSE2 :{REX} CVTPI2PD xmm, mm L: [diff. reg. set] T: 0.00ns= 0.000c 1113 SSE2 :{REX} CVTPD2PI mm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1114 SSE2 :{REX} CVTPD2PI + CVTPI2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1115 SSE2 :{REX} CVTTPD2PI mm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1116 SSE2 :{REX} CVTTPD2PI + CVTPI2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1117 SSE2 :{REX} CVTSI2SD xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 1118 SSE2 :{REX} CVTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1119 SSE2 :{REX} CVTSD2SI + CVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1120 SSE2 :{REX} CVTTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1121 SSE2 :{REX} CVTTSD2SI + CVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1122 AVX :{VEX} VCVTSI2SD xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 1123 AVX :{VEX} VCVTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1124 AVX :{VEX} VCVTSD2SI + VCVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1125 AVX :{VEX} VCVTTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1126 AVX :{VEX} VCVTTSD2SI + VCVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1127 AMD64 :{REX} CVTSI2SD xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 1128 AMD64 :{REX} CVTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1129 AMD64 :{REX} CVTSD2SI + CVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1130 AMD64 :{REX} CVTTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1131 AMD64 :{REX} CVTTSD2SI + CVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1132 AVX_X64 :{VEX} VCVTSI2SD xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 1133 AVX_X64 :{VEX} VCVTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1134 AVX_X64 :{VEX} VCVTSD2SI + VCVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1135 AVX_X64 :{VEX} VCVTTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1136 AVX_X64 :{VEX} VCVTTSD2SI + VCVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1137 SSE2 :{REX} CVTDQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1138 SSE2 :{REX} CVTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1139 SSE2 :{REX} CVTPD2DQ + CVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1140 SSE2 :{REX} CVTTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1141 SSE2 :{REX} CVTTPD2DQ + CVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1142 AVX :{VEX} VCVTDQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1143 AVX :{VEX} VCVTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1144 AVX :{VEX} VCVTPD2DQ + VCVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1145 AVX :{VEX} VCVTTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1146 AVX :{VEX} VCVTTPD2DQ + VCVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1147 SSE2 :{REX} CVTDQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1148 SSE2 :{REX} CVTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1149 SSE2 :{REX} CVTPS2DQ + CVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1150 SSE2 :{REX} CVTTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1151 SSE2 :{REX} CVTTPS2DQ + CVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1152 AVX :{VEX} VCVTDQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1153 AVX :{VEX} VCVTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1154 AVX :{VEX} VCVTPS2DQ + VCVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1155 AVX :{VEX} VCVTTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1156 AVX :{VEX} VCVTTPS2DQ + VCVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1157 SSE2 :{REX} CVTPS2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1158 SSE2 :{REX} CVTPD2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1159 SSE2 :{REX} CVTPD2PS + CVTPS2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1160 SSE2 :{REX} CVTSS2SD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1161 SSE2 :{REX} CVTSD2SS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1162 SSE2 :{REX} CVTSD2SS + CVTSS2SD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1163 AVX :{VEX} VCVTPS2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1164 AVX :{VEX} VCVTPD2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1165 AVX :{VEX} VCVTPD2PS + VCVTPS2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1166 AVX :{VEX} VCVTSS2SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1167 AVX :{VEX} VCVTSD2SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1168 AVX :{VEX} VCVTSD2SS + VCVTSS2SD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1169 SSE2 :{REX} MOVD r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1170 SSE2 :{REX} MOVD xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 1171 SSE2 :{REX} MOVD r32, xmm+MOVD xmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1172 AVX :{VEX} VMOVD r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1173 AVX :{VEX} VMOVD xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 1174 AVX :{VEX} VMOVD r32,xmm+VMOVD xmm,r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1175 AMD64 :{REX} MOVQ r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1176 AMD64 :{REX} MOVQ xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 1177 AMD64 :{REX} MOVQ r64, xmm+MOVD xmm, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1178 AVX_X64 :{VEX} VMOVQ r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1179 AVX_X64 :{VEX} VMOVQ xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 1180 AVX_X64 :{VEX} VMOVQ r64,xmm+VMOVD xmm,r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1181 SSE2 :{REX} MOVD xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 1182 SSE2 :{REX} MOVD [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 1183 SSE2 :{REX} MOVD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1184 AVX :{VEX} VMOVD xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 1185 AVX :{VEX} VMOVD [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 1186 AVX :{VEX} VMOVD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1187 SSE2 :{REX} MOVQ xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 1188 SSE2 :{REX} MOVQ [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 1189 SSE2 :{REX} MOVQ LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1190 AVX :{VEX} VMOVQ xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 1191 AVX :{VEX} VMOVQ [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 1192 AVX :{VEX} VMOVQ LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1193 SSE2 :{REX} MOVDQ2Q mm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1194 SSE2 :{REX} MOVQ2DQ xmm, mm L: [diff. reg. set] T: 0.00ns= 0.000c 1195 SSE2 :{REX} MOVDQ2Q + MOVQ2DQ xmm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1196 SSE2 :{REX} MOVDQA xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1197 SSE2 :{REX} MOVDQA xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1198 SSE2 :{REX} MOVDQA [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1199 SSE2 :{REX} MOVDQA LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1200 AVX :{VEX} VMOVDQA xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1201 AVX :{VEX} VMOVDQA xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1202 AVX :{VEX} VMOVDQA [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1203 AVX :{VEX} VMOVDQA LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1204 SSE2 :{REX} MOVDQU xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1205 SSE2 :{REX} MOVDQU xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1206 SSE2 :{REX} MOVDQU [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1207 SSE2 :{REX} MOVDQU aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1208 SSE2 :{REX} MOVDQU xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1209 SSE2 :{REX} MOVDQU [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 1210 SSE2 :{REX} MOVDQU unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1211 AVX :{VEX} VMOVDQU xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1212 AVX :{VEX} VMOVDQU xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1213 AVX :{VEX} VMOVDQU [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1214 AVX :{VEX} VMOVDQU aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1215 AVX :{VEX} VMOVDQU xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1216 AVX :{VEX} VMOVDQU [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 1217 AVX :{VEX} VMOVDQU unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1218 SSE4.1 :{REX} MOVNTDQA xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1219 SSE2 :{REX} MOVNTDQ [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1220 SSE4.1 :{REX} MOVNTDQA + MOVNTDQ xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1221 AVX :{VEX} VMOVNTDQA xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1222 AVX :{VEX} VMOVNTDQ [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 1223 AVX :{VEX} VMOVNTDQA + VMOVNTDQ xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1224 SSE2 :{REX} PMOVMSKB r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1225 AMD64 :{REX} PMOVMSKB r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1226 AVX :{VEX} VPMOVMSKB r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1227 AVX_X64 :{VEX} VPMOVMSKB r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 1228 SSE2 :{REX} MASKMOVDQU xmm, xmm L: [memory dep.] T: 0.00ns= 0.000c 1229 AVX :{VEX} VMASKMOVDQU xmm, xmm L: [memory dep.] T: 0.00ns= 0.000c 1230 SSE2 :{REX} PADDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1231 AVX :{VEX} VPADDB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1232 SSE2 :{REX} PADDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1233 AVX :{VEX} VPADDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1234 SSE2 :{REX} PADDD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1235 AVX :{VEX} VPADDD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1236 SSE2 :{REX} PADDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1237 AVX :{VEX} VPADDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1238 SSE2 :{REX} PADDSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1239 AVX :{VEX} VPADDSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1240 SSE2 :{REX} PADDSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1241 AVX :{VEX} VPADDSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1242 SSE2 :{REX} PADDUSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1243 AVX :{VEX} VPADDUSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1244 SSE2 :{REX} PADDUSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1245 AVX :{VEX} VPADDUSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1246 SSE2 :{REX} PSUBB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1247 SSE2 :{REX} PSUBB xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1248 AVX :{VEX} VPSUBB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1249 AVX :{VEX} VPSUBB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1250 SSE2 :{REX} PSUBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1251 SSE2 :{REX} PSUBW xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1252 AVX :{VEX} VPSUBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1253 AVX :{VEX} VPSUBW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1254 SSE2 :{REX} PSUBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1255 SSE2 :{REX} PSUBD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1256 AVX :{VEX} VPSUBD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1257 AVX :{VEX} VPSUBD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1258 SSE2 :{REX} PSUBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1259 SSE2 :{REX} PSUBQ xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1260 AVX :{VEX} VPSUBQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1261 AVX :{VEX} VPSUBQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1262 SSE2 :{REX} PSUBSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1263 SSE2 :{REX} PSUBSB xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1264 AVX :{VEX} VPSUBSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1265 AVX :{VEX} VPSUBSB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1266 SSE2 :{REX} PSUBSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1267 SSE2 :{REX} PSUBSW xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1268 AVX :{VEX} VPSUBSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1269 AVX :{VEX} VPSUBSW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1270 SSE2 :{REX} PSUBUSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1271 SSE2 :{REX} PSUBUSB xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1272 AVX :{VEX} VPSUBUSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1273 AVX :{VEX} VPSUBUSB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1274 SSE2 :{REX} PSUBUSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1275 SSE2 :{REX} PSUBUSW xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1276 AVX :{VEX} VPSUBUSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1277 AVX :{VEX} VPSUBUSW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1278 SSE2 :{REX} PCMPEQB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1279 SSE2 :{REX} PCMPEQB xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1280 AVX :{VEX} VPCMPEQB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1281 AVX :{VEX} VPCMPEQB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1282 SSE2 :{REX} PCMPEQW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1283 SSE2 :{REX} PCMPEQW xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1284 AVX :{VEX} VPCMPEQW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1285 AVX :{VEX} VPCMPEQW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1286 SSE2 :{REX} PCMPEQD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1287 SSE2 :{REX} PCMPEQD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1288 AVX :{VEX} VPCMPEQD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1289 AVX :{VEX} VPCMPEQD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1290 SSE4.1 :{REX} PCMPEQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1291 SSE4.1 :{REX} PCMPEQQ xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1292 AVX :{VEX} VPCMPEQQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1293 AVX :{VEX} VPCMPEQQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1294 SSE2 :{REX} PCMPGTB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1295 SSE2 :{REX} PCMPGTB xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1296 AVX :{VEX} VPCMPGTB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1297 AVX :{VEX} VPCMPGTB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1298 SSE2 :{REX} PCMPGTW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1299 SSE2 :{REX} PCMPGTW xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1300 AVX :{VEX} VPCMPGTW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1301 AVX :{VEX} VPCMPGTW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1302 SSE2 :{REX} PCMPGTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1303 SSE2 :{REX} PCMPGTD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1304 AVX :{VEX} VPCMPGTD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1305 AVX :{VEX} VPCMPGTD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1306 SSE4.2 :{REX} PCMPGTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1307 SSE4.2 :{REX} PCMPGTQ xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1308 AVX :{VEX} VPCMPGTQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1309 AVX :{VEX} VPCMPGTQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1310 SSE2 :{REX} PAND xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1311 SSE2 :{REX} PAND xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1312 AVX :{VEX} VPAND xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1313 AVX :{VEX} VPAND xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1314 SSE2 :{REX} PANDN xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1315 SSE2 :{REX} PANDN xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1316 AVX :{VEX} VPANDN xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1317 AVX :{VEX} VPANDN xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1318 SSE2 :{REX} POR xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1319 SSE2 :{REX} POR xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1320 AVX :{VEX} VPOR xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1321 AVX :{VEX} VPOR xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1322 SSE2 :{REX} PXOR xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1323 SSE2 :{REX} PXOR xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1324 AVX :{VEX} VPXOR xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1325 AVX :{VEX} VPXOR xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1326 SSE2 :{REX} PMULHW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1327 AVX :{VEX} VPMULHW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1328 SSE2 :{REX} PMULHUW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1329 AVX :{VEX} VPMULHUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1330 SSSE3 :{REX} PMULHRSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1331 AVX :{VEX} VPMULHRSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1332 SSE2 :{REX} PMULLW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1333 AVX :{VEX} VPMULLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1334 SSE4.1 :{REX} PMULLD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1335 AVX :{VEX} VPMULLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1336 SSE4.1 :{REX} PMULDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1337 AVX :{VEX} VPMULDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1338 SSE2 :{REX} PMULUDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1339 AVX :{VEX} VPMULUDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1340 SSSE3 :{REX} PMADDUBSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1341 AVX :{VEX} VPMADDUBSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1342 SSE2 :{REX} PMADDWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1343 AVX :{VEX} VPMADDWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1344 SSE2 :{REX} PSLLW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1345 AVX :{VEX} VPSLLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1346 SSE2 :{REX} PSLLW xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1347 AVX :{VEX} VPSLLW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1348 SSE2 :{REX} PSLLD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1349 AVX :{VEX} VPSLLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1350 SSE2 :{REX} PSLLD xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1351 AVX :{VEX} VPSLLD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1352 SSE2 :{REX} PSLLQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1353 AVX :{VEX} VPSLLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1354 SSE2 :{REX} PSLLQ xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1355 AVX :{VEX} VPSLLQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1356 SSE2 :{REX} PSLLDQ xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1357 AVX :{VEX} VPSLLDQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1358 SSE2 :{REX} PSRAW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1359 AVX :{VEX} VPSRAW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1360 SSE2 :{REX} PSRAW xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1361 AVX :{VEX} VPSRAW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1362 SSE2 :{REX} PSRAD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1363 AVX :{VEX} VPSRAD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1364 SSE2 :{REX} PSRAD xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1365 AVX :{VEX} VPSRAD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1366 SSE2 :{REX} PSRLW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1367 AVX :{VEX} VPSRLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1368 SSE2 :{REX} PSRLW xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1369 AVX :{VEX} VPSRLW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1370 SSE2 :{REX} PSRLD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1371 AVX :{VEX} VPSRLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1372 SSE2 :{REX} PSRLD xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1373 AVX :{VEX} VPSRLD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1374 SSE2 :{REX} PSRLQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1375 AVX :{VEX} VPSRLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1376 SSE2 :{REX} PSRLQ xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1377 AVX :{VEX} VPSRLQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1378 SSE2 :{REX} PSRLDQ xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1379 AVX :{VEX} VPSRLDQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1380 SSE2 :{REX} PUNPCKHBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1381 AVX :{VEX} VPUNPCKHBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1382 SSE2 :{REX} PUNPCKHWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1383 AVX :{VEX} VPUNPCKHWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1384 SSE2 :{REX} PUNPCKHDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1385 AVX :{VEX} VPUNPCKHDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1386 SSE2 :{REX} PUNPCKHQDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1387 AVX :{VEX} VPUNPCKHQDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1388 SSE2 :{REX} PUNPCKLBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1389 AVX :{VEX} VPUNPCKLBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1390 SSE2 :{REX} PUNPCKLWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1391 AVX :{VEX} VPUNPCKLWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1392 SSE2 :{REX} PUNPCKLDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1393 AVX :{VEX} VPUNPCKLDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1394 SSE2 :{REX} PUNPCKLQDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1395 AVX :{VEX} VPUNPCKLQDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1396 SSE2 :{REX} PACKSSWB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1397 AVX :{VEX} VPACKSSWB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1398 SSE2 :{REX} PACKUSWB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1399 AVX :{VEX} VPACKUSWB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1400 SSE2 :{REX} PACKSSDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1401 AVX :{VEX} VPACKSSDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1402 SSE4.1 :{REX} PACKUSDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1403 AVX :{VEX} VPACKUSDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1404 SSE2 :{REX} PAVGB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1405 AVX :{VEX} VPAVGB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1406 SSE2 :{REX} PAVGW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1407 AVX :{VEX} VPAVGW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1408 SSE4.1 :{REX} PEXTRB r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1409 SSE4.1 :{REX} PINSRB xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1410 SSE4.1 :{REX} PEXTRB + PINSRB r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1411 AVX :{VEX} VPEXTRB r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1412 AVX :{VEX} VPINSRB xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1413 AVX :{VEX} VPEXTRB + VPINSRB r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1414 SSE41_X64 :{REX} PEXTRB r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1415 SSE41_X64 :{REX} PEXTRB r64 + PINSRB r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1416 AVX_X64 :{VEX} VPEXTRB r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1417 AVX_X64 :{VEX} VPEXTRB r64 + VPINSRB r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1418 SSE2 :{REX} PEXTRW r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1419 SSE2 :{REX} PINSRW xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1420 SSE2 :{REX} PEXTRW + PINSRW r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1421 AVX :{VEX} VPEXTRW r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1422 AVX :{VEX} VPINSRW xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1423 AVX :{VEX} VPEXTRW + VPINSRW r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1424 AMD64 :{REX} PEXTRW r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1425 AMD64 :{REX} PEXTRW r64 + PINSRW r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1426 AVX_X64 :{VEX} VPEXTRW r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1427 AVX_X64 :{VEX} VPEXTRW r64 + VPINSRW r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1428 SSE4.1 :{REX} PEXTRD r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1429 SSE4.1 :{REX} PINSRD xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1430 SSE4.1 :{REX} PEXTRD + PINSRD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1431 AVX :{VEX} VPEXTRD r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1432 AVX :{VEX} VPINSRD xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1433 AVX :{VEX} VPEXTRD + VPINSRD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1434 SSE41_X64 :{REX} PEXTRQ r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1435 SSE41_X64 :{REX} PINSRQ xmm, r64, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1436 SSE41_X64 :{REX} PEXTRD + PINSRD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1437 AVX_X64 :{VEX} VPEXTRQ r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1438 AVX_X64 :{VEX} VPINSRQ xmm, r64, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1439 AVX_X64 :{VEX} VPEXTRQ + VPINSRQ r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1440 SSE4.1 :{REX} EXTRACTPS r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1441 AVX :{VEX} VEXTRACTPS r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1442 SSE41_X64 :{REX} EXTRACTPS r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1443 AVX_X64 :{VEX} VEXTRACTPS r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 1444 SSE4.1 :{REX} INSERTPS xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1445 AVX :{VEX} VINSERTPS xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1446 SSE4A :{REX} EXTRQ xmm, im8, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1447 SSE4A :{REX} EXTRQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1448 SSE4A :{REX} INSERTQ xmm, xmm, im8, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1449 SSE4A :{REX} INSERTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1450 SSE2 :{REX} PMAXUB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1451 AVX :{VEX} VPMAXUB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1452 SSE4.1 :{REX} PMAXSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1453 AVX :{VEX} VPMAXSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1454 SSE4.1 :{REX} PMAXUW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1455 AVX :{VEX} VPMAXUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1456 SSE2 :{REX} PMAXSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1457 AVX :{VEX} VPMAXSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1458 SSE4.1 :{REX} PMAXUD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1459 AVX :{VEX} VPMAXUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1460 SSE4.1 :{REX} PMAXSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1461 AVX :{VEX} VPMAXSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1462 SSE2 :{REX} PMINUB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1463 AVX :{VEX} VPMINUB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1464 SSE4.1 :{REX} PMINSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1465 AVX :{VEX} VPMINSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1466 SSE4.1 :{REX} PMINUW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1467 AVX :{VEX} VPMINUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1468 SSE2 :{REX} PMINSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1469 AVX :{VEX} VPMINSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1470 SSE4.1 :{REX} PMINUD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1471 AVX :{VEX} VPMINUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1472 SSE4.1 :{REX} PMINSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1473 AVX :{VEX} VPMINSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1474 SSE2 :{REX} PSADBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1475 AVX :{VEX} VPSADBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1476 SSSE3 :{REX} PSHUFB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1477 AVX :{VEX} VPSHUFB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1478 SSE2 :{REX} PSHUFLW xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1479 AVX :{VEX} VPSHUFLW xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1480 SSE2 :{REX} PSHUFHW xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1481 AVX :{VEX} VPSHUFHW xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1482 SSE2 :{REX} PSHUFD xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1483 AVX :{VEX} VPSHUFD xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1484 SSE3 :{REX} ADDSUBPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1485 AVX :{VEX} VADDSUBPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1486 SSE3 :{REX} ADDSUBPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1487 AVX :{VEX} VADDSUBPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1488 SSE3 :{REX} HADDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1489 AVX :{VEX} VHADDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1490 SSE3 :{REX} HADDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1491 AVX :{VEX} VHADDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1492 SSE3 :{REX} HSUBPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1493 AVX :{VEX} VHSUBPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1494 SSE3 :{REX} HSUBPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1495 AVX :{VEX} VHSUBPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1496 SSE3 :{REX} MOVSLDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1497 AVX :{VEX} VMOVSLDUP xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1498 SSE3 :{REX} MOVSHDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1499 AVX :{VEX} VMOVSHDUP xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1500 SSE3 :{REX} MOVDDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1501 AVX :{VEX} VMOVDDUP xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1502 SSE3 :{REX} LDDQU xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1503 AVX :{VEX} VLDDQU xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1504 SSSE3 :{REX} PABSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1505 AVX :{VEX} VPABSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1506 SSSE3 :{REX} PABSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1507 AVX :{VEX} VPABSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1508 SSSE3 :{REX} PABSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1509 AVX :{VEX} VPABSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1510 SSSE3 :{REX} PALIGNR xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1511 AVX :{VEX} VPALIGNR xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1512 SSSE3 :{REX} PHADDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1513 AVX :{VEX} VPHADDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1514 SSSE3 :{REX} PHADDD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1515 AVX :{VEX} VPHADDD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1516 SSSE3 :{REX} PHADDSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1517 AVX :{VEX} VPHADDSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1518 SSSE3 :{REX} PHSUBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1519 AVX :{VEX} VPHSUBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1520 SSSE3 :{REX} PHSUBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1521 AVX :{VEX} VPHSUBD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1522 SSSE3 :{REX} PHSUBSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1523 AVX :{VEX} VPHSUBSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1524 SSSE3 :{REX} PSIGNB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1525 AVX :{VEX} VPSIGNB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1526 SSSE3 :{REX} PSIGNW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1527 AVX :{VEX} VPSIGNW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1528 SSSE3 :{REX} PSIGND xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1529 AVX :{VEX} VPSIGND xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1530 SSE4.1 :{REX} BLENDPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1531 AVX :{VEX} VBLENDPS xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1532 SSE4.1 :{REX} BLENDVPS xmm, xmm, L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1533 AVX :{VEX} VBLENDVPS xmm, xmm, xmm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1534 SSE4.1 :{REX} BLENDPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1535 AVX :{VEX} VBLENDPD xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1536 SSE4.1 :{REX} BLENDVPD xmm, xmm, L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1537 AVX :{VEX} VBLENDVPD xmm, xmm, xmm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1538 SSE4.1 :{REX} PBLENDW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1539 AVX :{VEX} VPBLENDW xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1540 SSE4.1 :{REX} PBLENDVB xmm, xmm, L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1541 AVX :{VEX} VPBLENDVB xmm, xmm, xmm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1542 SSE4.1 :{REX} DPPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1543 AVX :{VEX} VDPPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1544 SSE4.1 :{REX} DPPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1545 AVX :{VEX} VDPPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1546 SSE4.1 :{REX} MPSADBW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1547 AVX :{VEX} VMPSADBW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1548 SSE4.1 :{REX} PHMINPOSUW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1549 AVX :{VEX} VPHMINPOSUW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1550 SSE4.1 :{REX} PMOVSXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1551 AVX :{VEX} VPMOVSXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1552 SSE4.1 :{REX} PMOVSXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1553 AVX :{VEX} VPMOVSXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1554 SSE4.1 :{REX} PMOVSXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1555 AVX :{VEX} VPMOVSXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1556 SSE4.1 :{REX} PMOVSXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1557 AVX :{VEX} VPMOVSXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1558 SSE4.1 :{REX} PMOVSXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1559 AVX :{VEX} VPMOVSXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1560 SSE4.1 :{REX} PMOVSXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1561 AVX :{VEX} VPMOVSXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1562 SSE4.1 :{REX} PMOVZXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1563 AVX :{VEX} VPMOVZXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1564 SSE4.1 :{REX} PMOVZXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1565 AVX :{VEX} VPMOVZXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1566 SSE4.1 :{REX} PMOVZXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1567 AVX :{VEX} VPMOVZXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1568 SSE4.1 :{REX} PMOVZXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1569 AVX :{VEX} VPMOVZXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1570 SSE4.1 :{REX} PMOVZXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1571 AVX :{VEX} VPMOVZXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1572 SSE4.1 :{REX} PMOVZXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1573 AVX :{VEX} VPMOVZXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1574 SSE4.1 :{REX} PTEST xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1575 AVX :{VEX} VPTEST xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1576 AVX :{VEX} VTESTPS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1577 AVX :{VEX} VTESTPD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 1578 SSE4.1 :{REX} ROUNDSS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1579 AVX :{VEX} VROUNDSS xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1580 SSE4.1 :{REX} ROUNDPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1581 AVX :{VEX} VROUNDPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1582 SSE4.1 :{REX} ROUNDSD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1583 AVX :{VEX} VROUNDSD xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1584 SSE4.1 :{REX} ROUNDPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1585 AVX :{VEX} VROUNDPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1586 AVX :{VEX} VBROADCASTSS xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 1587 SSE4.2 :{REX} PCMPESTRI xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1588 AVX :{VEX} VPCMPESTRI xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1589 SSE4.2 :{REX} PCMPESTRM xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1590 AVX :{VEX} VPCMPESTRM xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1591 SSE4.2 :{REX} PCMPISTRI xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1592 AVX :{VEX} VPCMPISTRI xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1593 SSE4.2 :{REX} PCMPISTRM xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1594 AVX :{VEX} VPCMPISTRM xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1595 CLMUL :{REX} PCLMULQDQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1596 AVX_CLMUL :{VEX} VPCLMULQDQ xmm,xmm,xmm,im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1597 AESNI :{REX} AESENC xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1598 AVX_AESNI :{VEX} VAESENC xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1599 AESNI :{REX} AESENCLAST xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1600 AVX_AESNI :{VEX} VAESENCLAST xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1601 AESNI :{REX} AESDEC xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1602 AVX_AESNI :{VEX} VAESDEC xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1603 AESNI :{REX} AESDECLAST xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1604 AVX_AESNI :{VEX} VAESDECLAST xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1605 AESNI :{REX} AESIMC xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1606 AVX_AESNI :{VEX} VAESIMC xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1607 AESNI :{REX} AESKEYGEN xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1608 AVX_AESNI :{VEX} VAESKEYGEN xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1609 FMA4 :{VEX} VFMADDSS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1610 FMA3 :{VEX} VFMADD132SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1611 FMA3 :{VEX} VFMADD213SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1612 FMA3 :{VEX} VFMADD231SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1613 FMA4 :{VEX} VFMADDPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1614 FMA3 :{VEX} VFMADD132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1615 FMA3 :{VEX} VFMADD213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1616 FMA3 :{VEX} VFMADD231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1617 FMA4 :{VEX} VFMSUBSS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1618 FMA3 :{VEX} VFMSUB132SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1619 FMA3 :{VEX} VFMSUB213SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1620 FMA3 :{VEX} VFMSUB231SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1621 FMA4 :{VEX} VFMSUBPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1622 FMA3 :{VEX} VFMSUB132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1623 FMA3 :{VEX} VFMSUB213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1624 FMA3 :{VEX} VFMSUB231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1625 FMA4 :{VEX} VFNMADDSS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1626 FMA3 :{VEX} VFNMADD132SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1627 FMA3 :{VEX} VFNMADD213SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1628 FMA3 :{VEX} VFNMADD231SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1629 FMA4 :{VEX} VFNMADDPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1630 FMA3 :{VEX} VFNMADD132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1631 FMA3 :{VEX} VFNMADD213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1632 FMA3 :{VEX} VFNMADD231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1633 FMA4 :{VEX} VFNMSUBSS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1634 FMA3 :{VEX} VFNMSUB132SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1635 FMA3 :{VEX} VFNMSUB213SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1636 FMA3 :{VEX} VFNMSUB231SS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1637 FMA4 :{VEX} VFNMSUBPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1638 FMA3 :{VEX} VFNMSUB132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1639 FMA3 :{VEX} VFNMSUB213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1640 FMA3 :{VEX} VFNMSUB231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1641 FMA4 :{VEX} VFMADDSUBPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1642 FMA3 :{VEX} VFMADDSUB132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1643 FMA3 :{VEX} VFMADDSUB213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1644 FMA3 :{VEX} VFMADDSUB231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1645 FMA4 :{VEX} VFMSUBADDPS xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1646 FMA3 :{VEX} VFMSUBADD132PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1647 FMA3 :{VEX} VFMSUBADD213PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1648 FMA3 :{VEX} VFMSUBADD231PS xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1649 FMA4 :{VEX} VFMADDSD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1650 FMA3 :{VEX} VFMADD132SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1651 FMA3 :{VEX} VFMADD213SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1652 FMA3 :{VEX} VFMADD231SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1653 FMA4 :{VEX} VFMADDPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1654 FMA3 :{VEX} VFMADD132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1655 FMA3 :{VEX} VFMADD213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1656 FMA3 :{VEX} VFMADD231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1657 FMA4 :{VEX} VFMSUBSD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1658 FMA3 :{VEX} VFMSUB132SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1659 FMA3 :{VEX} VFMSUB213SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1660 FMA3 :{VEX} VFMSUB231SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1661 FMA4 :{VEX} VFMSUBPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1662 FMA3 :{VEX} VFMSUB132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1663 FMA3 :{VEX} VFMSUB213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1664 FMA3 :{VEX} VFMSUB231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1665 FMA4 :{VEX} VFNMADDSD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1666 FMA3 :{VEX} VFNMADD132SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1667 FMA3 :{VEX} VFNMADD213SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1668 FMA3 :{VEX} VFNMADD231SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1669 FMA4 :{VEX} VFNMADDPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1670 FMA3 :{VEX} VFNMADD132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1671 FMA3 :{VEX} VFNMADD213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1672 FMA3 :{VEX} VFNMADD231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1673 FMA4 :{VEX} VFNMSUBSD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1674 FMA3 :{VEX} VFNMSUB132SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1675 FMA3 :{VEX} VFNMSUB213SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1676 FMA3 :{VEX} VFNMSUB231SD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1677 FMA4 :{VEX} VFNMSUBPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1678 FMA3 :{VEX} VFNMSUB132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1679 FMA3 :{VEX} VFNMSUB213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1680 FMA3 :{VEX} VFNMSUB231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1681 FMA4 :{VEX} VFMADDSUBPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1682 FMA3 :{VEX} VFMADDSUB132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1683 FMA3 :{VEX} VFMADDSUB213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1684 FMA3 :{VEX} VFMADDSUB231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1685 FMA4 :{VEX} VFMSUBADDPD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1686 FMA3 :{VEX} VFMSUBADD132PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1687 FMA3 :{VEX} VFMSUBADD213PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1688 FMA3 :{VEX} VFMSUBADD231PD xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1689 XOP :{XOP} VFRCZSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1690 XOP :{XOP} VFRCZPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1691 XOP :{XOP} VFRCZSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1692 XOP :{XOP} VFRCZPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1693 XOP :{XOP} VPCMOV xmm, xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1694 XOP :{XOP} VPCOMB xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1695 XOP :{XOP} VPCOMB xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1696 XOP :{XOP} VPCOMW xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1697 XOP :{XOP} VPCOMW xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1698 XOP :{XOP} VPCOMD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1699 XOP :{XOP} VPCOMD xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1700 XOP :{XOP} VPCOMQ xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1701 XOP :{XOP} VPCOMQ xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1702 XOP :{XOP} VPCOMUB xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1703 XOP :{XOP} VPCOMUB xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1704 XOP :{XOP} VPCOMUW xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1705 XOP :{XOP} VPCOMUW xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1706 XOP :{XOP} VPCOMUD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1707 XOP :{XOP} VPCOMUD xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1708 XOP :{XOP} VPCOMUQ xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1709 XOP :{XOP} VPCOMUQ xm1, xm1, xm2, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1710 XOP :{VEX} VPERMIL2PS xm,xm,xm,xm,im L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1711 XOP :{VEX} VPERMIL2PD xm,xm,xm,xm,im L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1712 XOP :{XOP} VPHADDBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1713 XOP :{XOP} VPHADDBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1714 XOP :{XOP} VPHADDBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1715 XOP :{XOP} VPHADDWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1716 XOP :{XOP} VPHADDWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1717 XOP :{XOP} VPHADDDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1718 XOP :{XOP} VPHADDUBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1719 XOP :{XOP} VPHADDUBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1720 XOP :{XOP} VPHADDUBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1721 XOP :{XOP} VPHADDUWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1722 XOP :{XOP} VPHADDUWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1723 XOP :{XOP} VPHADDUDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1724 XOP :{XOP} VPHSUBBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1725 XOP :{XOP} VPHSUBWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1726 XOP :{XOP} VPHSUBDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1727 XOP :{XOP} VPMACSWW xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1728 XOP :{XOP} VPMACSWW xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1729 XOP :{XOP} VPMACSWD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1730 XOP :{XOP} VPMACSWD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1731 XOP :{XOP} VPMACSDD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1732 XOP :{XOP} VPMACSDD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1733 XOP :{XOP} VPMACSDQL xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1734 XOP :{XOP} VPMACSDQL xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1735 XOP :{XOP} VPMACSDQH xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1736 XOP :{XOP} VPMACSDQH xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1737 XOP :{XOP} VPMACSSWW xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1738 XOP :{XOP} VPMACSSWW xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1739 XOP :{XOP} VPMACSSWD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1740 XOP :{XOP} VPMACSSWD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1741 XOP :{XOP} VPMACSSDD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1742 XOP :{XOP} VPMACSSDD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1743 XOP :{XOP} VPMACSSDQL xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1744 XOP :{XOP} VPMACSSDQL xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1745 XOP :{XOP} VPMACSSDQH xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1746 XOP :{XOP} VPMACSSDQH xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1747 XOP :{XOP} VPMADCSWD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1748 XOP :{XOP} VPMADCSWD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1749 XOP :{XOP} VPMADCSSWD xmm,xmm,xmm,xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1750 XOP :{XOP} VPMADCSSWD xm1,xm2,xm2,xm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1751 XOP :{XOP} VPPERM xmm, xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1752 XOP :{XOP} VPROTB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1753 XOP :{XOP} VPROTB xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1754 XOP :{XOP} VPROTW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1755 XOP :{XOP} VPROTW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1756 XOP :{XOP} VPROTD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1757 XOP :{XOP} VPROTD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1758 XOP :{XOP} VPROTQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1759 XOP :{XOP} VPROTQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1760 XOP :{XOP} VPSHAB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1761 XOP :{XOP} VPSHAW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1762 XOP :{XOP} VPSHAD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1763 XOP :{XOP} VPSHAQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1764 XOP :{XOP} VPSHLB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1765 XOP :{XOP} VPSHLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1766 XOP :{XOP} VPSHLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1767 XOP :{XOP} VPSHLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1768 F16C :{VEX} VCVTPS2PH xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1769 F16C :{VEX} VCVTPH2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1770 AVX :{VEX} VMOVAPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1771 AVX :{VEX} VMOVAPS ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1772 AVX :{VEX} VMOVAPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1773 AVX :{VEX} VMOVAPS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1774 AVX :{VEX} VMOVUPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1775 AVX :{VEX} VMOVUPS ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1776 AVX :{VEX} VMOVUPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1777 AVX :{VEX} VMOVUPS aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1778 AVX :{VEX} VMOVUPS ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1779 AVX :{VEX} VMOVUPS [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 1780 AVX :{VEX} VMOVUPS unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1781 AVX :{VEX} VMOVSLDUP ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1782 AVX :{VEX} VMOVSHDUP ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1783 AVX :{VEX} VMOVNTPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1784 AVX :{VEX} VMOVMSKPS r32, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 1785 AVX :{VEX} VMASKMOVPS ymm,ymm,[m256+4] L: [memory dep.] T: 0.00ns= 0.000c 1786 AVX :{VEX} VMASKMOVPS [m256+4],ymm,ymm L: [memory dep.] T: 0.00ns= 0.000c 1787 AVX :{VEX} VMASKMOVPS unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1788 AVX :{VEX} VUNPCKLPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1789 AVX :{VEX} VUNPCKHPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1790 AVX :{VEX} VSHUFPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1791 AVX :{VEX} VPERMILPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1792 AVX :{VEX} VPERMILPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1793 AVX :{VEX} VCMPPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1794 AVX :{VEX} VADDSUBPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1795 AVX :{VEX} VHSUBPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1796 AVX :{VEX} VHADDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1797 AVX :{VEX} VSUBPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1798 AVX :{VEX} VADDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1799 AVX :{VEX} VMULPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1800 AVX :{VEX} VMULPS+VADDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1801 AVX :{VEX} VMULPS ymm1.. VADDPS ymm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1802 AVX :{VEX} VMAXPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1803 AVX :{VEX} VMINPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1804 AVX :{VEX} VANDNPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1805 AVX :{VEX} VANDNPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1806 AVX :{VEX} VANDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1807 AVX :{VEX} VANDPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1808 AVX :{VEX} VORPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1809 AVX :{VEX} VORPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1810 AVX :{VEX} VXORPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1811 AVX :{VEX} VXORPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1812 AVX :{VEX} VDIVPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1813 AVX :{VEX} VDIVPS (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1814 AVX :{VEX} VDIVPS (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1815 AVX :{VEX} VDIVPS (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1816 AVX :{VEX} VDIVPS (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1817 AVX :{VEX} VSQRTPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1818 AVX :{VEX} VSQRTPS (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1819 AVX :{VEX} VSQRTPS (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1820 AVX :{VEX} VRCPPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1821 AVX :{VEX} VRSQRTPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1822 AVX :{VEX} VBLENDPS ymm, ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1823 AVX :{VEX} VBLENDVPS ymm, ymm, ymm, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1824 AVX :{VEX} VDPPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1825 AVX :{VEX} VTESTPS ymm, ymm L: [no true dep.] T: 0.00ns= 0.000c 1826 AVX :{VEX} VROUNDPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1827 AVX :{VEX} VMOVAPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1828 AVX :{VEX} VMOVAPD ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1829 AVX :{VEX} VMOVAPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1830 AVX :{VEX} VMOVAPD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1831 AVX :{VEX} VMOVUPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1832 AVX :{VEX} VMOVUPD ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1833 AVX :{VEX} VMOVUPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1834 AVX :{VEX} VMOVUPD aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1835 AVX :{VEX} VMOVUPD ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1836 AVX :{VEX} VMOVUPD [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 1837 AVX :{VEX} VMOVUPD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1838 AVX :{VEX} VMOVDDUP ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1839 AVX :{VEX} VMOVNTPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1840 AVX :{VEX} VMOVMSKPD r32, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 1841 AVX :{VEX} VMASKMOVPD ymm,ymm,[m256+4] L: [memory dep.] T: 0.00ns= 0.000c 1842 AVX :{VEX} VMASKMOVPD [m256+4],ymm,ymm L: [memory dep.] T: 0.00ns= 0.000c 1843 AVX :{VEX} VMASKMOVPD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1844 AVX :{VEX} VUNPCKLPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1845 AVX :{VEX} VUNPCKHPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1846 AVX :{VEX} VSHUFPD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1847 AVX :{VEX} VPERMILPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1848 AVX :{VEX} VPERMILPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1849 AVX :{VEX} VCMPPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1850 AVX :{VEX} VADDSUBPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1851 AVX :{VEX} VHSUBPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1852 AVX :{VEX} VHADDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1853 AVX :{VEX} VSUBPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1854 AVX :{VEX} VADDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1855 AVX :{VEX} VMULPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1856 AVX :{VEX} VMULPD+VADDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1857 AVX :{VEX} VMULPD ymm1.. VADDPD ymm2.. L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1858 AVX :{VEX} VMAXPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1859 AVX :{VEX} VMINPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1860 AVX :{VEX} VANDNPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1861 AVX :{VEX} VANDNPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1862 AVX :{VEX} VANDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1863 AVX :{VEX} VANDPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1864 AVX :{VEX} VORPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1865 AVX :{VEX} VORPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1866 AVX :{VEX} VXORPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1867 AVX :{VEX} VXORPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1868 AVX :{VEX} VDIVPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1869 AVX :{VEX} VDIVPD (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1870 AVX :{VEX} VDIVPD (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1871 AVX :{VEX} VDIVPD (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1872 AVX :{VEX} VDIVPD (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1873 AVX :{VEX} VSQRTPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1874 AVX :{VEX} VSQRTPD (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1875 AVX :{VEX} VSQRTPD (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1876 AVX :{VEX} VBLENDPD ymm, ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1877 AVX :{VEX} VBLENDVPD ymm, ymm, ymm, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1878 AVX :{VEX} VCVTDQ2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1879 AVX :{VEX} VCVTPD2DQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1880 AVX :{VEX} VCVTPD2DQ + VCVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1881 AVX :{VEX} VCVTTPD2DQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1882 AVX :{VEX} VCVTTPD2DQ + VCVTDQ2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1883 AVX :{VEX} VCVTDQ2PS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1884 AVX :{VEX} VCVTPS2DQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1885 AVX :{VEX} VCVTPS2DQ + VCVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1886 AVX :{VEX} VCVTTPS2DQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1887 AVX :{VEX} VCVTTPS2DQ + VCVTDQ2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1888 AVX :{VEX} VCVTPS2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1889 AVX :{VEX} VCVTPD2PS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1890 AVX :{VEX} VCVTPD2PS + VCVTPS2PD L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1891 AVX :{VEX} VTESTPD ymm, ymm L: [no true dep.] T: 0.00ns= 0.000c 1892 AVX :{VEX} VROUNDPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1893 AVX :{VEX} VBROADCASTSS ymm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 1894 AVX :{VEX} VBROADCASTSD ymm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 1895 AVX :{VEX} VBROADCASTF128 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 1896 AVX :{VEX} VEXTRACTF128 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1897 AVX :{VEX} VINSERTF128 ym, ym, xm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1898 AVX :{VEX} VPERM2F128 ym, ym, ym, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1899 AVX :{VEX} VMOVDQA ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1900 AVX :{VEX} VMOVDQA ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1901 AVX :{VEX} VMOVDQA [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1902 AVX :{VEX} VMOVDQA LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1903 AVX :{VEX} VMOVDQU ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1904 AVX :{VEX} VMOVDQU ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 1905 AVX :{VEX} VMOVDQU [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1906 AVX :{VEX} VMOVDQU aligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1907 AVX :{VEX} VMOVDQU ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1908 AVX :{VEX} VMOVDQU [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 1909 AVX :{VEX} VMOVDQU unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1910 AVX :{VEX} VMOVNTDQ [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 1911 AVX :{VEX} VLDDQU ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 1912 AVX :{VEX} VZEROUPPER L: [no true dep.] T: 0.00ns= 0.000c 1913 AVX :{VEX} VZEROALL L: [no true dep.] T: 0.00ns= 0.000c 1914 FMA4 :{VEX} VFMADDPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1915 FMA3 :{VEX} VFMADD132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1916 FMA3 :{VEX} VFMADD213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1917 FMA3 :{VEX} VFMADD231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1918 FMA4 :{VEX} VFMSUBPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1919 FMA3 :{VEX} VFMSUB132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1920 FMA3 :{VEX} VFMSUB213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1921 FMA3 :{VEX} VFMSUB231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1922 FMA4 :{VEX} VFNMADDPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1923 FMA3 :{VEX} VFNMADD132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1924 FMA3 :{VEX} VFNMADD213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1925 FMA3 :{VEX} VFNMADD231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1926 FMA4 :{VEX} VFNMSUBPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1927 FMA3 :{VEX} VFNMSUB132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1928 FMA3 :{VEX} VFNMSUB213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1929 FMA3 :{VEX} VFNMSUB231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1930 FMA4 :{VEX} VFMADDSUBPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1931 FMA3 :{VEX} VFMADDSUB132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1932 FMA3 :{VEX} VFMADDSUB213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1933 FMA3 :{VEX} VFMADDSUB231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1934 FMA4 :{VEX} VFMSUBADDPS ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1935 FMA3 :{VEX} VFMSUBADD132PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1936 FMA3 :{VEX} VFMSUBADD213PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1937 FMA3 :{VEX} VFMSUBADD231PS ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1938 FMA4 :{VEX} VFMADDPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1939 FMA3 :{VEX} VFMADD132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1940 FMA3 :{VEX} VFMADD213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1941 FMA3 :{VEX} VFMADD231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1942 FMA4 :{VEX} VFMSUBPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1943 FMA3 :{VEX} VFMSUB132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1944 FMA3 :{VEX} VFMSUB213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1945 FMA3 :{VEX} VFMSUB231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1946 FMA4 :{VEX} VFNMADDPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1947 FMA3 :{VEX} VFNMADD132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1948 FMA3 :{VEX} VFNMADD213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1949 FMA3 :{VEX} VFNMADD231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1950 FMA4 :{VEX} VFNMSUBPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1951 FMA3 :{VEX} VFNMSUB132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1952 FMA3 :{VEX} VFNMSUB213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1953 FMA3 :{VEX} VFNMSUB231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1954 FMA4 :{VEX} VFMADDSUBPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1955 FMA3 :{VEX} VFMADDSUB132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1956 FMA3 :{VEX} VFMADDSUB213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1957 FMA3 :{VEX} VFMADDSUB231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1958 FMA4 :{VEX} VFMSUBADDPD ymm,ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1959 FMA3 :{VEX} VFMSUBADD132PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1960 FMA3 :{VEX} VFMSUBADD213PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1961 FMA3 :{VEX} VFMSUBADD231PD ymm,ymm,ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1962 XOP :{XOP} VFRCZSD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1963 XOP :{XOP} VFRCZPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1964 XOP :{XOP} VPCMOV ymm, ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1965 XOP :{VEX} VPERMIL2PS ym,ym,ym,ym,im L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1966 XOP :{VEX} VPERMIL2PD ym,ym,ym,ym,im L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1967 F16C :{VEX} VCVTPS2PH + VCVTPH2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1968 F16C :{VEX} VCVTPS2PH xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1969 F16C :{VEX} VCVTPH2PS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1970 F16C :{VEX} VCVTPS2PH + VCVTPH2PS L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1971 RDRAND :{REX} RDRAND r16 L: [no true dep.] T: 0.00ns= 0.000c 1972 RDRAND :{REX} RDRAND r32 L: [no true dep.] T: 0.00ns= 0.000c 1973 RDRAND_X64 :{REX} RDRAND r64 L: [no true dep.] T: 0.00ns= 0.000c 1974 X86 :{REX} MOV+ADD r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1975 X86 :{REX} MOV+ADD r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1976 X86 :{REX} MOV+ADD r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1977 AMD64 :{REX} MOV+ADD r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1978 MMX :{REX} MOVQ+PADDB mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1979 MMX :{REX} MOVQ+PADDW mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1980 MMX :{REX} MOVQ+PADDD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1981 SSE2 :{REX} MOVQ+PADDQ mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1982 3DNOW :{REX} MOVQ+PFADD mm, mm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1983 SSE :{REX} MOVSS+ADDSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1984 AVX :{VEX} VMOVSS+VADDSS xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1985 SSE :{REX} MOVAPS+ADDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1986 AVX :{VEX} VMOVAPS+VADDPS xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1987 SSE2 :{REX} MOVSD+ADDSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1988 AVX :{VEX} VMOVSD+VADDSD xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1989 SSE2 :{REX} MOVAPD+ADDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1990 AVX :{VEX} VMOVAPD+VADDPD xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1991 SSE2 :{REX} MOVDQA+PADDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1992 SSE2 :{REX} MOVDQA+PADDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1993 SSE2 :{REX} MOVDQA+PADDD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1994 SSE2 :{REX} MOVDQA+PADDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1995 AVX :{VEX} VMOVDQA+VPADDB xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1996 AVX :{VEX} VMOVDQA+VPADDW xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1997 AVX :{VEX} VMOVDQA+VPADDD xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1998 AVX :{VEX} VMOVDQA+VPADDQ xm, xm, xm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 1999 AVX :{VEX} VMOVAPS+VADDPS ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2000 AVX :{VEX} VMOVAPD+VADDPD ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2001 RDSEED :{REX} RDSEED r16 L: [no true dep.] T: 0.00ns= 0.000c 2002 RDSEED :{REX} RDSEED r32 L: [no true dep.] T: 0.00ns= 0.000c 2003 RDSEED_X64 :{REX} RDSEED r64 L: [no true dep.] T: 0.00ns= 0.000c 2004 BMI :{VEX} ANDN r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2005 BMI_X64 :{VEX} ANDN r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2006 BMI :{VEX} BEXTR r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2007 BMI_X64 :{VEX} BEXTR r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2008 BMI :{VEX} BLSI r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2009 BMI_X64 :{VEX} BLSI r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2010 BMI :{VEX} BLSMSK r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2011 BMI_X64 :{VEX} BLSMSK r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2012 BMI :{VEX} BLSR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2013 BMI_X64 :{VEX} BLSR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2014 BMI :{REX} TZCNT r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2015 BMI :{REX} TZCNT r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2016 BMI_X64 :{REX} TZCNT r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2017 BMI2 :{VEX} BZHI r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2018 BMI2_X64 :{VEX} BZHI r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2019 BMI2 :{VEX} MULX r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2020 BMI2_X64 :{VEX} MULX r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2021 BMI2 :{VEX} PDEP r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2022 BMI2_X64 :{VEX} PDEP r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2023 BMI2 :{VEX} PEXT r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2024 BMI2_X64 :{VEX} PEXT r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2025 BMI2 :{VEX} RORX r32, r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2026 BMI2_X64 :{VEX} RORX r64, r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2027 BMI2 :{VEX} SARX r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2028 BMI2_X64 :{VEX} SARX r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2029 BMI2 :{VEX} SHLX r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2030 BMI2_X64 :{VEX} SHLX r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2031 BMI2 :{VEX} SHRX r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2032 BMI2_X64 :{VEX} SHRX r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2033 TBM :{XOP} BEXTR r32, r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2034 TBM_X64 :{XOP} BEXTR r64, r64, imm64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2035 TBM :{XOP} BLCFILL r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2036 TBM_X64 :{XOP} BLCFILL r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2037 TBM :{XOP} BLCI r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2038 TBM_X64 :{XOP} BLCI r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2039 TBM :{XOP} BLCIC r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2040 TBM_X64 :{XOP} BLCIC r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2041 TBM :{XOP} BLCMSK r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2042 TBM_X64 :{XOP} BLCMSK r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2043 TBM :{XOP} BLCS r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2044 TBM_X64 :{XOP} BLCS r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2045 TBM :{XOP} BLSFILL r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2046 TBM_X64 :{XOP} BLSFILL r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2047 TBM :{XOP} BLSIC r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2048 TBM_X64 :{XOP} BLSIC r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2049 TBM :{XOP} T1MSKC r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2050 TBM_X64 :{XOP} T1MSKC r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2051 TBM :{XOP} TZMSK r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2052 TBM_X64 :{XOP} TZMSK r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2053 AVX2 :{VEX} VMOVNTDQA ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 2054 AVX2 :{VEX} VMOVNTDQA + VMOVNTDQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2055 AVX2 :{VEX} VPMOVMSKB r32, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 2056 AVX2_X64 :{VEX} VPMOVMSKB r64, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 2057 AVX2 :{VEX} VPADDB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2058 AVX2 :{VEX} VPADDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2059 AVX2 :{VEX} VPADDD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2060 AVX2 :{VEX} VPADDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2061 AVX2 :{VEX} VPADDSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2062 AVX2 :{VEX} VPADDSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2063 AVX2 :{VEX} VPADDUSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2064 AVX2 :{VEX} VPADDUSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2065 AVX2 :{VEX} VPSUBB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2066 AVX2 :{VEX} VPSUBB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2067 AVX2 :{VEX} VPSUBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2068 AVX2 :{VEX} VPSUBW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2069 AVX2 :{VEX} VPSUBD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2070 AVX2 :{VEX} VPSUBD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2071 AVX2 :{VEX} VPSUBQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2072 AVX2 :{VEX} VPSUBQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2073 AVX2 :{VEX} VPSUBSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2074 AVX2 :{VEX} VPSUBSB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2075 AVX2 :{VEX} VPSUBSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2076 AVX2 :{VEX} VPSUBSW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2077 AVX2 :{VEX} VPSUBUSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2078 AVX2 :{VEX} VPSUBUSB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2079 AVX2 :{VEX} VPSUBUSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2080 AVX2 :{VEX} VPSUBUSW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2081 AVX2 :{VEX} VPCMPEQB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2082 AVX2 :{VEX} VPCMPEQB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2083 AVX2 :{VEX} VPCMPEQW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2084 AVX2 :{VEX} VPCMPEQW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2085 AVX2 :{VEX} VPCMPEQD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2086 AVX2 :{VEX} VPCMPEQD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2087 AVX2 :{VEX} VPCMPEQQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2088 AVX2 :{VEX} VPCMPEQQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2089 AVX2 :{VEX} VPCMPGTB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2090 AVX2 :{VEX} VPCMPGTB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2091 AVX2 :{VEX} VPCMPGTW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2092 AVX2 :{VEX} VPCMPGTW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2093 AVX2 :{VEX} VPCMPGTD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2094 AVX2 :{VEX} VPCMPGTD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2095 AVX2 :{VEX} VPCMPGTQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2096 AVX2 :{VEX} VPCMPGTQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2097 AVX2 :{VEX} VPAND ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2098 AVX2 :{VEX} VPAND ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2099 AVX2 :{VEX} VPANDN ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2100 AVX2 :{VEX} VPANDN ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2101 AVX2 :{VEX} VPOR ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2102 AVX2 :{VEX} VPOR ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2103 AVX2 :{VEX} VPXOR ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2104 AVX2 :{VEX} VPXOR ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2105 AVX2 :{VEX} VPMULHW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2106 AVX2 :{VEX} VPMULHUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2107 AVX2 :{VEX} VPMULHRSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2108 AVX2 :{VEX} VPMULLW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2109 AVX2 :{VEX} VPMULLD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2110 AVX2 :{VEX} VPMULDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2111 AVX2 :{VEX} VPMULUDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2112 AVX2 :{VEX} VPMADDUBSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2113 AVX2 :{VEX} VPMADDWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2114 AVX2 :{VEX} VPSLLW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2115 AVX2 :{VEX} VPSLLW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2116 AVX2 :{VEX} VPSLLD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2117 AVX2 :{VEX} VPSLLD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2118 AVX2 :{VEX} VPSLLQ ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2119 AVX2 :{VEX} VPSLLQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2120 AVX2 :{VEX} VPSLLDQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2121 AVX2 :{VEX} VPSRAW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2122 AVX2 :{VEX} VPSRAW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2123 AVX2 :{VEX} VPSRAD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2124 AVX2 :{VEX} VPSRAD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2125 AVX2 :{VEX} VPSRLW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2126 AVX2 :{VEX} VPSRLW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2127 AVX2 :{VEX} VPSRLD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2128 AVX2 :{VEX} VPSRLD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2129 AVX2 :{VEX} VPSRLQ ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2130 AVX2 :{VEX} VPSRLQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2131 AVX2 :{VEX} VPSRLDQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2132 AVX2 :{VEX} VPUNPCKHBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2133 AVX2 :{VEX} VPUNPCKHWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2134 AVX2 :{VEX} VPUNPCKHDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2135 AVX2 :{VEX} VPUNPCKHQDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2136 AVX2 :{VEX} VPUNPCKLBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2137 AVX2 :{VEX} VPUNPCKLWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2138 AVX2 :{VEX} VPUNPCKLDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2139 AVX2 :{VEX} VPUNPCKLQDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2140 AVX2 :{VEX} VPACKSSWB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2141 AVX2 :{VEX} VPACKUSWB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2142 AVX2 :{VEX} VPACKSSDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2143 AVX2 :{VEX} VPACKUSDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2144 AVX2 :{VEX} VPAVGB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2145 AVX2 :{VEX} VPAVGW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2146 AVX2 :{VEX} VPMAXUB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2147 AVX2 :{VEX} VPMAXSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2148 AVX2 :{VEX} VPMAXUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2149 AVX2 :{VEX} VPMAXSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2150 AVX2 :{VEX} VPMAXUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2151 AVX2 :{VEX} VPMAXSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2152 AVX2 :{VEX} VPMINUB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2153 AVX2 :{VEX} VPMINSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2154 AVX2 :{VEX} VPMINUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2155 AVX2 :{VEX} VPMINSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2156 AVX2 :{VEX} VPMINUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2157 AVX2 :{VEX} VPMINSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2158 AVX2 :{VEX} VPSADBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2159 AVX2 :{VEX} VPSHUFB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2160 AVX2 :{VEX} VPSHUFLW ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2161 AVX2 :{VEX} VPSHUFHW ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2162 AVX2 :{VEX} VPSHUFD ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2163 AVX2 :{VEX} VPABSB ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2164 AVX2 :{VEX} VPABSW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2165 AVX2 :{VEX} VPABSD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2166 AVX2 :{VEX} VPALIGNR ymm, ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2167 AVX2 :{VEX} VPHADDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2168 AVX2 :{VEX} VPHADDD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2169 AVX2 :{VEX} VPHADDSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2170 AVX2 :{VEX} VPHSUBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2171 AVX2 :{VEX} VPHSUBD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2172 AVX2 :{VEX} VPHSUBSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2173 AVX2 :{VEX} VPSIGNB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2174 AVX2 :{VEX} VPSIGNW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2175 AVX2 :{VEX} VPSIGND ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2176 AVX2 :{VEX} VPBLENDW ymm, ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2177 AVX2 :{VEX} VPBLENDVB ymm, ymm, ymm, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2178 AVX2 :{VEX} VPBLENDD xmm, xmm, xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2179 AVX2 :{VEX} VPBLENDD ymm, ymm, ymm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2180 AVX2 :{VEX} VMPSADBW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2181 AVX2 :{VEX} VPMOVSXBW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2182 AVX2 :{VEX} VPMOVSXBD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2183 AVX2 :{VEX} VPMOVSXBQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2184 AVX2 :{VEX} VPMOVSXWD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2185 AVX2 :{VEX} VPMOVSXWQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2186 AVX2 :{VEX} VPMOVSXDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2187 AVX2 :{VEX} VPMOVZXBW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2188 AVX2 :{VEX} VPMOVZXBD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2189 AVX2 :{VEX} VPMOVZXBQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2190 AVX2 :{VEX} VPMOVZXWD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2191 AVX2 :{VEX} VPMOVZXWQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2192 AVX2 :{VEX} VPMOVZXDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2193 AVX2 :{VEX} VPMASKMOVD xmm,xmm,[m128+4] L: [memory dep.] T: 0.00ns= 0.000c 2194 AVX2 :{VEX} VPMASKMOVD [m128+4],xmm,xmm L: [memory dep.] T: 0.00ns= 0.000c 2195 AVX2 :{VEX} VPMASKMOVD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2196 AVX2 :{VEX} VPMASKMOVQ xmm,xmm,[m128+4] L: [memory dep.] T: 0.00ns= 0.000c 2197 AVX2 :{VEX} VPMASKMOVQ [m128+4],xmm,xmm L: [memory dep.] T: 0.00ns= 0.000c 2198 AVX2 :{VEX} VPMASKMOVQ unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2199 AVX2 :{VEX} VPMASKMOVD ymm,ymm,[m256+4] L: [memory dep.] T: 0.00ns= 0.000c 2200 AVX2 :{VEX} VPMASKMOVD [m256+4],ymm,ymm L: [memory dep.] T: 0.00ns= 0.000c 2201 AVX2 :{VEX} VPMASKMOVD unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2202 AVX2 :{VEX} VPMASKMOVQ ymm,ymm,[m256+4] L: [memory dep.] T: 0.00ns= 0.000c 2203 AVX2 :{VEX} VPMASKMOVQ [m256+4],ymm,ymm L: [memory dep.] T: 0.00ns= 0.000c 2204 AVX2 :{VEX} VPMASKMOVQ unaligned LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2205 AVX2 :{VEX} VBROADCASTSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2206 AVX2 :{VEX} VBROADCASTSS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2207 AVX2 :{VEX} VBROADCASTSD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2208 AVX2 :{VEX} VPBROADCASTB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2209 AVX2 :{VEX} VPBROADCASTB ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2210 AVX2 :{VEX} VPBROADCASTW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2211 AVX2 :{VEX} VPBROADCASTW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2212 AVX2 :{VEX} VPBROADCASTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2213 AVX2 :{VEX} VPBROADCASTD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2214 AVX2 :{VEX} VPBROADCASTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2215 AVX2 :{VEX} VPBROADCASTQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2216 AVX2 :{VEX} VBROADCASTI128 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 2217 AVX2 :{VEX} VEXTRACTI128 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2218 AVX2 :{VEX} VINSERTI128 ym, ym, xm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2219 AVX2 :{VEX} VPERM2I128 ym, ym, ym, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2220 AVX2 :{VEX} VPERMD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2221 AVX2 :{VEX} VPERMQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2222 AVX2 :{VEX} VPERMPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2223 AVX2 :{VEX} VPERMPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2224 AVX2 :{VEX} VPSLLVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2225 AVX2 :{VEX} VPSLLVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2226 AVX2 :{VEX} VPSLLVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2227 AVX2 :{VEX} VPSLLVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2228 AVX2 :{VEX} VPSRLVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2229 AVX2 :{VEX} VPSRLVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2230 AVX2 :{VEX} VPSRLVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2231 AVX2 :{VEX} VPSRLVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2232 AVX2 :{VEX} VPSRAVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2233 AVX2 :{VEX} VPSRAVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2234 ADX :{REX} ADCX r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2235 ADX_X64 :{REX} ADCX r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2236 ADX :{REX} ADOX r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2237 ADX_X64 :{REX} ADOX r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2238 CLFLUSH :{REX} CLFLUSH [mem] L: [memory dep.] T: 0.00ns= 0.000c 2239 CLFLUSHOPT :{REX} CLFLUSHOPT [mem] L: [memory dep.] T: 0.00ns= 0.000c 2240 PREFETCHWT1 :{REX} PREFETCHWT1 [mem] L: [memory dep.] T: 0.00ns= 0.000c 2241 SHA :{REX} SHA1RNDS4 xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2242 SHA :{REX} SHA1NEXTE xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2243 SHA :{REX} SHA1MSG1 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2244 SHA :{REX} SHA1MSG2 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2245 SHA :{REX} SHA256RNDS2 xm, xm, L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2246 SHA :{REX} SHA256MSG1 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2247 SHA :{REX} SHA256MSG2 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2248 X86 :{REX} MOV r1_8, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2249 X86 :{REX} MOV r1_16, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2250 X86 :{REX} MOV r1_32, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2251 AMD64 :{REX} MOV r1_64, r2_64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2252 X86 :{REX} MOVSX r1_16, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2253 X86 :{REX} MOVSX r1_32, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2254 AMD64 :{REX} MOVSX r1_64, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2255 X86 :{REX} MOVSX r1_32, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2256 AMD64 :{REX} MOVSX r1_64, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2257 AMD64 :{REX} MOVSXD r1_64, r2_32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2258 X86 :{REX} MOVZX r1_16, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2259 X86 :{REX} MOVZX r1_32, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2260 AMD64 :{REX} MOVZX r1_64, r2_8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2261 X86 :{REX} MOVZX r1_32, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2262 AMD64 :{REX} MOVZX r1_64, r2_16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2263 MMX :{REX} MOVQ mm1, mm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2264 SSE :{REX} MOVSS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2265 AVX :{VEX} VMOVSS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2266 SSE :{REX} MOVAPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2267 AVX :{VEX} VMOVAPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2268 SSE :{REX} MOVUPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2269 AVX :{VEX} VMOVUPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2270 SSE2 :{REX} MOVSD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2271 AVX :{VEX} VMOVSD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2272 SSE2 :{REX} MOVAPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2273 AVX :{VEX} VMOVAPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2274 SSE2 :{REX} MOVUPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2275 AVX :{VEX} VMOVUPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2276 SSE2 :{REX} MOVDQA xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2277 AVX :{VEX} VMOVDQA xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2278 SSE2 :{REX} MOVDQU xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2279 AVX :{VEX} VMOVDQU xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2280 AVX :{VEX} VMOVAPS ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2281 AVX :{VEX} VMOVUPS ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2282 AVX :{VEX} VMOVAPD ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2283 AVX :{VEX} VMOVUPD ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2284 AVX :{VEX} VMOVDQA ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2285 AVX :{VEX} VMOVDQU ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2286 AVX2 :{VEX} VPADDD+VADDPS ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2287 AVX2 :{VEX} VPADDQ+VADDPD ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2288 AVX2 :{VEX} VCMPPS+VPADDD ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2289 AVX2 :{VEX} VCMPPD+VPADDQ ym, ym, ym L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2290 SSE : 4xADDPS xm1,xm1 4x xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2291 SSE : 4xMULPS xm1,xm1 4x xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2292 SSE2 : 4xADDPD xm1,xm1 4x xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2293 SSE2 : 4xMULPD xm1,xm1 4x xm2,xm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2294 LNOP : LNOP3 [eax], eax L: [no true dep.] T: 0.00ns= 0.000c 2295 LNOP : LNOP4 [eax+disp8], eax L: [no true dep.] T: 0.00ns= 0.000c 2296 LNOP : LNOP5 [SIB+disp8], eax L: [no true dep.] T: 0.00ns= 0.000c 2297 LNOP : LNOP6 [SIB+disp8], ax L: [no true dep.] T: 0.00ns= 0.000c 2298 LNOP : LNOP7 [eax+disp32], eax L: [no true dep.] T: 0.00ns= 0.000c 2299 LNOP : LNOP8 [SIB+disp32], eax L: [no true dep.] T: 0.00ns= 0.000c 2300 LNOP : LNOP9 [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2301 LNOP : 2x66 LNOPA [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2302 LNOP : 3x66 LNOPB [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2303 LNOP : 4x66 LNOPC [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2304 LNOP : 5x66 LNOPD [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2305 LNOP : 6x66 LNOPE [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2306 LNOP : 7x66 LNOPF [SIB+disp32], ax L: [no true dep.] T: 0.00ns= 0.000c 2307 3DNOW : 4xPFADD m1, m1 4x m2, m2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2308 3DNOW : 4xPFMUL m1, m1 4x m2, m2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2309 AVX2 :{VEX} VGATHERDPS xmm, [xm32], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2310 AVX2 :{VEX} VGATHERDPS ymm, [ym32], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2311 AVX2 :{VEX} VGATHERQPS xmm, [xm64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2312 AVX2 :{VEX} VGATHERQPS xmm, [ym64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2313 AVX2 :{VEX} VGATHERDPD xmm, [xm32], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2314 AVX2 :{VEX} VGATHERDPD ymm, [xm32], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2315 AVX2 :{VEX} VGATHERQPD xmm, [xm64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2316 AVX2 :{VEX} VGATHERQPD ymm, [ym64], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2317 AVX2 :{VEX} VPGATHERDD xmm, [xm32], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2318 AVX2 :{VEX} VPGATHERDD ymm, [ym32], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2319 AVX2 :{VEX} VPGATHERQD xmm, [xm64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2320 AVX2 :{VEX} VPGATHERQD xmm, [ym64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2321 AVX2 :{VEX} VPGATHERDQ xmm, [xm32], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2322 AVX2 :{VEX} VPGATHERDQ ymm, [xm32], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2323 AVX2 :{VEX} VPGATHERQQ xmm, [xm64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2324 AVX2 :{VEX} VPGATHERQQ ymm, [ym64], ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2325 CLZERO : CLZERO [rAX] L: [memory dep.] T: 0.00ns= 0.000c 2326 CLWB :{REX} CLWB [mem] L: [memory dep.] T: 0.00ns= 0.000c 2327 PCOMMIT : PCOMMIT L: [no true dep.] T: 0.00ns= 0.000c 2328 OSPKE : RDPKRU L: [no true dep.] T: 0.00ns= 0.000c 2329 OSPKE : WRPKRU L: [no true dep.] T: 0.00ns= 0.000c 2330 RDPID :{REX} RDPID r64 L: [no true dep.] T: 0.00ns= 0.000c 2331 AVX512DQ :{VEX} KADDB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2332 AVX512DQ :{VEX} KADDW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2333 AVX512BW :{VEX} KADDD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2334 AVX512BW :{VEX} KADDQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2335 AVX512DQ :{VEX} KANDB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2336 AVX512F :{VEX} KANDW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2337 AVX512BW :{VEX} KANDD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2338 AVX512BW :{VEX} KANDQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2339 AVX512DQ :{VEX} KANDNB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2340 AVX512F :{VEX} KANDNW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2341 AVX512BW :{VEX} KANDND k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2342 AVX512BW :{VEX} KANDNQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2343 AVX512DQ :{VEX} KMOVB k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2344 AVX512DQ :{VEX} KMOVB k, [mem8] L: [memory dep.] T: 0.00ns= 0.000c 2345 AVX512DQ :{VEX} KMOVB [mem8], k L: [memory dep.] T: 0.00ns= 0.000c 2346 AVX512DQ :{VEX} KMOVB k, [mem8] + KMOVB [mem8], k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2347 AVX512DQ :{VEX} KMOVB k, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2348 AVX512DQ :{VEX} KMOVB r32, k L: [diff. reg. set] T: 0.00ns= 0.000c 2349 AVX512DQ :{VEX} KMOVB k, r32 + KMOVB r32, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2350 AVX512F :{VEX} KMOVW k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2351 AVX512F :{VEX} KMOVW k, [mem16] L: [memory dep.] T: 0.00ns= 0.000c 2352 AVX512F :{VEX} KMOVW [mem16], k L: [memory dep.] T: 0.00ns= 0.000c 2353 AVX512F :{VEX} KMOVW k, [mem16] + KMOVW [mem16], k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2354 AVX512F :{VEX} KMOVW k, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2355 AVX512F :{VEX} KMOVW r32, k L: [diff. reg. set] T: 0.00ns= 0.000c 2356 AVX512F :{VEX} KMOVW k, r32 + KMOVW r32, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2357 AVX512BW :{VEX} KMOVD k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2358 AVX512BW :{VEX} KMOVD k, [mem32] L: [memory dep.] T: 0.00ns= 0.000c 2359 AVX512BW :{VEX} KMOVD [mem32], k L: [memory dep.] T: 0.00ns= 0.000c 2360 AVX512BW :{VEX} KMOVD k, [mem32] + KMOVD [mem32], k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2361 AVX512BW :{VEX} KMOVD k, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2362 AVX512BW :{VEX} KMOVD r32, k L: [diff. reg. set] T: 0.00ns= 0.000c 2363 AVX512BW :{VEX} KMOVD k, r32 + KMOVD r32, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2364 AVX512BW :{VEX} KMOVQ k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2365 AVX512BW :{VEX} KMOVQ k, [mem64] L: [memory dep.] T: 0.00ns= 0.000c 2366 AVX512BW :{VEX} KMOVQ [mem64], k L: [memory dep.] T: 0.00ns= 0.000c 2367 AVX512BW :{VEX} KMOVQ k, [mem64] + KMOVQ [mem64], k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2368 AVX512BW_X64 :{VEX} KMOVQ k, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 2369 AVX512BW_X64 :{VEX} KMOVQ r64, k L: [diff. reg. set] T: 0.00ns= 0.000c 2370 AVX512BW_X64 :{VEX} KMOVQ k, r64 + KMOVQ r64, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2371 AVX512DQ :{VEX} KNOTB k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2372 AVX512F :{VEX} KNOTW k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2373 AVX512BW :{VEX} KNOTD k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2374 AVX512BW :{VEX} KNOTQ k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2375 AVX512DQ :{VEX} KORB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2376 AVX512F :{VEX} KORW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2377 AVX512BW :{VEX} KORD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2378 AVX512BW :{VEX} KORQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2379 AVX512DQ :{VEX} KORTESTB k, k L: [no true dep.] T: 0.00ns= 0.000c 2380 AVX512F :{VEX} KORTESTW k, k L: [no true dep.] T: 0.00ns= 0.000c 2381 AVX512BW :{VEX} KORTESTD k, k L: [no true dep.] T: 0.00ns= 0.000c 2382 AVX512BW :{VEX} KORTESTQ k, k L: [no true dep.] T: 0.00ns= 0.000c 2383 AVX512DQ :{VEX} KSHIFTLB k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2384 AVX512F :{VEX} KSHIFTLW k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2385 AVX512BW :{VEX} KSHIFTLD k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2386 AVX512BW :{VEX} KSHIFTLQ k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2387 AVX512DQ :{VEX} KSHIFTRB k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2388 AVX512F :{VEX} KSHIFTRW k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2389 AVX512BW :{VEX} KSHIFTRD k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2390 AVX512BW :{VEX} KSHIFTRQ k, k, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2391 AVX512DQ :{VEX} KTESTB k, k L: [no true dep.] T: 0.00ns= 0.000c 2392 AVX512DQ :{VEX} KTESTW k, k L: [no true dep.] T: 0.00ns= 0.000c 2393 AVX512BW :{VEX} KTESTD k, k L: [no true dep.] T: 0.00ns= 0.000c 2394 AVX512BW :{VEX} KTESTQ k, k L: [no true dep.] T: 0.00ns= 0.000c 2395 AVX512F :{VEX} KUNPCKBW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2396 AVX512BW :{VEX} KUNPCKWD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2397 AVX512BW :{VEX} KUNPCKDQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2398 AVX512DQ :{VEX} KXNORB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2399 AVX512F :{VEX} KXNORW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2400 AVX512BW :{VEX} KXNORD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2401 AVX512BW :{VEX} KXNORQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2402 AVX512DQ :{VEX} KXORB k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2403 AVX512F :{VEX} KXORW k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2404 AVX512BW :{VEX} KXORD k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2405 AVX512BW :{VEX} KXORQ k, k, k L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2406 AVX512F :{EVEX} VADDSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2407 AVX512VL :{EVEX} VADDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2408 AVX512VL :{EVEX} VADDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2409 AVX512F :{EVEX} VADDPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2410 AVX512F :{EVEX} VADDSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2411 AVX512VL :{EVEX} VADDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2412 AVX512VL :{EVEX} VADDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2413 AVX512F :{EVEX} VADDPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2414 AVX512F :{EVEX} VSUBSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2415 AVX512VL :{EVEX} VSUBPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2416 AVX512VL :{EVEX} VSUBPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2417 AVX512F :{EVEX} VSUBPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2418 AVX512F :{EVEX} VSUBSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2419 AVX512VL :{EVEX} VSUBPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2420 AVX512VL :{EVEX} VSUBPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2421 AVX512F :{EVEX} VSUBPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2422 AVX512F :{EVEX} VMULSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2423 AVX512VL :{EVEX} VMULPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2424 AVX512VL :{EVEX} VMULPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2425 AVX512F :{EVEX} VMULPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2426 AVX512F :{EVEX} VMULSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2427 AVX512VL :{EVEX} VMULPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2428 AVX512VL :{EVEX} VMULPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2429 AVX512F :{EVEX} VMULPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2430 AVX512F :{EVEX} VFMADD132SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2431 AVX512VL :{EVEX} VFMADD132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2432 AVX512VL :{EVEX} VFMADD132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2433 AVX512F :{EVEX} VFMADD132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2434 AVX512F :{EVEX} VFMADD132SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2435 AVX512VL :{EVEX} VFMADD132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2436 AVX512VL :{EVEX} VFMADD132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2437 AVX512F :{EVEX} VFMADD132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2438 AVX512F :{EVEX} VFMADD213SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2439 AVX512VL :{EVEX} VFMADD213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2440 AVX512VL :{EVEX} VFMADD213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2441 AVX512F :{EVEX} VFMADD213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2442 AVX512F :{EVEX} VFMADD213SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2443 AVX512VL :{EVEX} VFMADD213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2444 AVX512VL :{EVEX} VFMADD213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2445 AVX512F :{EVEX} VFMADD213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2446 AVX512F :{EVEX} VFMADD231SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2447 AVX512VL :{EVEX} VFMADD231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2448 AVX512VL :{EVEX} VFMADD231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2449 AVX512F :{EVEX} VFMADD231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2450 AVX512F :{EVEX} VFMADD231SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2451 AVX512VL :{EVEX} VFMADD231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2452 AVX512VL :{EVEX} VFMADD231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2453 AVX512F :{EVEX} VFMADD231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2454 AVX512F :{EVEX} VFMSUB132SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2455 AVX512VL :{EVEX} VFMSUB132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2456 AVX512VL :{EVEX} VFMSUB132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2457 AVX512F :{EVEX} VFMSUB132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2458 AVX512F :{EVEX} VFMSUB132SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2459 AVX512VL :{EVEX} VFMSUB132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2460 AVX512VL :{EVEX} VFMSUB132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2461 AVX512F :{EVEX} VFMSUB132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2462 AVX512F :{EVEX} VFMSUB213SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2463 AVX512VL :{EVEX} VFMSUB213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2464 AVX512VL :{EVEX} VFMSUB213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2465 AVX512F :{EVEX} VFMSUB213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2466 AVX512F :{EVEX} VFMSUB213SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2467 AVX512VL :{EVEX} VFMSUB213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2468 AVX512VL :{EVEX} VFMSUB213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2469 AVX512F :{EVEX} VFMSUB213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2470 AVX512F :{EVEX} VFMSUB231SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2471 AVX512VL :{EVEX} VFMSUB231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2472 AVX512VL :{EVEX} VFMSUB231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2473 AVX512F :{EVEX} VFMSUB231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2474 AVX512F :{EVEX} VFMSUB231SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2475 AVX512VL :{EVEX} VFMSUB231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2476 AVX512VL :{EVEX} VFMSUB231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2477 AVX512F :{EVEX} VFMSUB231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2478 AVX512F :{EVEX} VFNMADD132SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2479 AVX512VL :{EVEX} VFNMADD132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2480 AVX512VL :{EVEX} VFNMADD132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2481 AVX512F :{EVEX} VFNMADD132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2482 AVX512F :{EVEX} VFNMADD132SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2483 AVX512VL :{EVEX} VFNMADD132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2484 AVX512VL :{EVEX} VFNMADD132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2485 AVX512F :{EVEX} VFNMADD132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2486 AVX512F :{EVEX} VFNMADD213SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2487 AVX512VL :{EVEX} VFNMADD213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2488 AVX512VL :{EVEX} VFNMADD213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2489 AVX512F :{EVEX} VFNMADD213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2490 AVX512F :{EVEX} VFNMADD213SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2491 AVX512VL :{EVEX} VFNMADD213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2492 AVX512VL :{EVEX} VFNMADD213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2493 AVX512F :{EVEX} VFNMADD213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2494 AVX512F :{EVEX} VFNMADD231SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2495 AVX512VL :{EVEX} VFNMADD231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2496 AVX512VL :{EVEX} VFNMADD231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2497 AVX512F :{EVEX} VFNMADD231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2498 AVX512F :{EVEX} VFNMADD231SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2499 AVX512VL :{EVEX} VFNMADD231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2500 AVX512VL :{EVEX} VFNMADD231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2501 AVX512F :{EVEX} VFNMADD231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2502 AVX512F :{EVEX} VFNMSUB132SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2503 AVX512VL :{EVEX} VFNMSUB132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2504 AVX512VL :{EVEX} VFNMSUB132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2505 AVX512F :{EVEX} VFNMSUB132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2506 AVX512F :{EVEX} VFNMSUB132SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2507 AVX512VL :{EVEX} VFNMSUB132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2508 AVX512VL :{EVEX} VFNMSUB132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2509 AVX512F :{EVEX} VFNMSUB132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2510 AVX512F :{EVEX} VFNMSUB213SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2511 AVX512VL :{EVEX} VFNMSUB213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2512 AVX512VL :{EVEX} VFNMSUB213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2513 AVX512F :{EVEX} VFNMSUB213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2514 AVX512F :{EVEX} VFNMSUB213SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2515 AVX512VL :{EVEX} VFNMSUB213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2516 AVX512VL :{EVEX} VFNMSUB213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2517 AVX512F :{EVEX} VFNMSUB213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2518 AVX512F :{EVEX} VFNMSUB231SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2519 AVX512VL :{EVEX} VFNMSUB231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2520 AVX512VL :{EVEX} VFNMSUB231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2521 AVX512F :{EVEX} VFNMSUB231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2522 AVX512F :{EVEX} VFNMSUB231SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2523 AVX512VL :{EVEX} VFNMSUB231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2524 AVX512VL :{EVEX} VFNMSUB231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2525 AVX512F :{EVEX} VFNMSUB231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2526 AVX512VL :{EVEX} VFMADDSUB132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2527 AVX512VL :{EVEX} VFMADDSUB132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2528 AVX512F :{EVEX} VFMADDSUB132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2529 AVX512VL :{EVEX} VFMADDSUB132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2530 AVX512VL :{EVEX} VFMADDSUB132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2531 AVX512F :{EVEX} VFMADDSUB132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2532 AVX512VL :{EVEX} VFMADDSUB213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2533 AVX512VL :{EVEX} VFMADDSUB213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2534 AVX512F :{EVEX} VFMADDSUB213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2535 AVX512VL :{EVEX} VFMADDSUB213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2536 AVX512VL :{EVEX} VFMADDSUB213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2537 AVX512F :{EVEX} VFMADDSUB213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2538 AVX512VL :{EVEX} VFMADDSUB231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2539 AVX512VL :{EVEX} VFMADDSUB231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2540 AVX512F :{EVEX} VFMADDSUB231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2541 AVX512VL :{EVEX} VFMADDSUB231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2542 AVX512VL :{EVEX} VFMADDSUB231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2543 AVX512F :{EVEX} VFMADDSUB231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2544 AVX512VL :{EVEX} VFMSUBADD132PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2545 AVX512VL :{EVEX} VFMSUBADD132PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2546 AVX512F :{EVEX} VFMSUBADD132PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2547 AVX512VL :{EVEX} VFMSUBADD132PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2548 AVX512VL :{EVEX} VFMSUBADD132PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2549 AVX512F :{EVEX} VFMSUBADD132PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2550 AVX512VL :{EVEX} VFMSUBADD213PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2551 AVX512VL :{EVEX} VFMSUBADD213PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2552 AVX512F :{EVEX} VFMSUBADD213PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2553 AVX512VL :{EVEX} VFMSUBADD213PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2554 AVX512VL :{EVEX} VFMSUBADD213PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2555 AVX512F :{EVEX} VFMSUBADD213PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2556 AVX512VL :{EVEX} VFMSUBADD231PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2557 AVX512VL :{EVEX} VFMSUBADD231PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2558 AVX512F :{EVEX} VFMSUBADD231PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2559 AVX512VL :{EVEX} VFMSUBADD231PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2560 AVX512VL :{EVEX} VFMSUBADD231PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2561 AVX512F :{EVEX} VFMSUBADD231PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2562 AVX512F :{EVEX} VDIVSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2563 AVX512F :{EVEX} VDIVSS xmm (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2564 AVX512F :{EVEX} VDIVSS xmm (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2565 AVX512F :{EVEX} VDIVSS xmm (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2566 AVX512F :{EVEX} VDIVSS xmm (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2567 AVX512VL :{EVEX} VDIVPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2568 AVX512VL :{EVEX} VDIVPS xmm (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2569 AVX512VL :{EVEX} VDIVPS xmm (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2570 AVX512VL :{EVEX} VDIVPS xmm (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2571 AVX512VL :{EVEX} VDIVPS xmm (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2572 AVX512VL :{EVEX} VDIVPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2573 AVX512VL :{EVEX} VDIVPS ymm (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2574 AVX512VL :{EVEX} VDIVPS ymm (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2575 AVX512VL :{EVEX} VDIVPS ymm (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2576 AVX512VL :{EVEX} VDIVPS ymm (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2577 AVX512F :{EVEX} VDIVPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2578 AVX512F :{EVEX} VDIVPS zmm (0.0f/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2579 AVX512F :{EVEX} VDIVPS zmm (x/1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2580 AVX512F :{EVEX} VDIVPS zmm (x/2.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2581 AVX512F :{EVEX} VDIVPS zmm (x/0.5f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2582 AVX512F :{EVEX} VDIVSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2583 AVX512F :{EVEX} VDIVSD xmm (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2584 AVX512F :{EVEX} VDIVSD xmm (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2585 AVX512F :{EVEX} VDIVSD xmm (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2586 AVX512F :{EVEX} VDIVSD xmm (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2587 AVX512VL :{EVEX} VDIVPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2588 AVX512VL :{EVEX} VDIVPD xmm (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2589 AVX512VL :{EVEX} VDIVPD xmm (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2590 AVX512VL :{EVEX} VDIVPD xmm (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2591 AVX512VL :{EVEX} VDIVPD xmm (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2592 AVX512VL :{EVEX} VDIVPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2593 AVX512VL :{EVEX} VDIVPD ymm (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2594 AVX512VL :{EVEX} VDIVPD ymm (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2595 AVX512VL :{EVEX} VDIVPD ymm (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2596 AVX512VL :{EVEX} VDIVPD ymm (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2597 AVX512F :{EVEX} VDIVPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2598 AVX512F :{EVEX} VDIVPD zmm (0.0/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2599 AVX512F :{EVEX} VDIVPD zmm (x/1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2600 AVX512F :{EVEX} VDIVPD zmm (x/2.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2601 AVX512F :{EVEX} VDIVPD zmm (x/0.5) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2602 AVX512F :{EVEX} VSQRTSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2603 AVX512F :{EVEX} VSQRTSS xmm, (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2604 AVX512F :{EVEX} VSQRTSS xmm, (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2605 AVX512VL :{EVEX} VSQRTPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2606 AVX512VL :{EVEX} VSQRTPS xmm (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2607 AVX512VL :{EVEX} VSQRTPS xmm (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2608 AVX512VL :{EVEX} VSQRTPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2609 AVX512VL :{EVEX} VSQRTPS ymm (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2610 AVX512VL :{EVEX} VSQRTPS ymm (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2611 AVX512F :{EVEX} VSQRTPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2612 AVX512F :{EVEX} VSQRTPS zmm (0.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2613 AVX512F :{EVEX} VSQRTPS zmm (1.0f) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2614 AVX512F :{EVEX} VSQRTSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2615 AVX512F :{EVEX} VSQRTSD xmm, (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2616 AVX512F :{EVEX} VSQRTSD xmm, (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2617 AVX512VL :{EVEX} VSQRTPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2618 AVX512VL :{EVEX} VSQRTPD xmm (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2619 AVX512VL :{EVEX} VSQRTPD xmm (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2620 AVX512VL :{EVEX} VSQRTPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2621 AVX512VL :{EVEX} VSQRTPD ymm (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2622 AVX512VL :{EVEX} VSQRTPD ymm (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2623 AVX512F :{EVEX} VSQRTPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2624 AVX512F :{EVEX} VSQRTPD zmm (0.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2625 AVX512F :{EVEX} VSQRTPD zmm (1.0) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2626 AVX512F :{EVEX} VRCP14SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2627 AVX512VL :{EVEX} VRCP14PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2628 AVX512VL :{EVEX} VRCP14PS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2629 AVX512F :{EVEX} VRCP14PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2630 AVX512F :{EVEX} VRCP14SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2631 AVX512VL :{EVEX} VRCP14PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2632 AVX512VL :{EVEX} VRCP14PD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2633 AVX512F :{EVEX} VRCP14PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2634 AVX512ER :{EVEX} VRCP28SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2635 AVX512ER :{EVEX} VRCP28PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2636 AVX512ER :{EVEX} VRCP28SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2637 AVX512ER :{EVEX} VRCP28PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2638 AVX512F :{EVEX} VRSQRT14SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2639 AVX512VL :{EVEX} VRSQRT14PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2640 AVX512VL :{EVEX} VRSQRT14PS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2641 AVX512F :{EVEX} VRSQRT14PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2642 AVX512F :{EVEX} VRSQRT14SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2643 AVX512VL :{EVEX} VRSQRT14PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2644 AVX512VL :{EVEX} VRSQRT14PD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2645 AVX512F :{EVEX} VRSQRT14PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2646 AVX512ER :{EVEX} VRSQRT28SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2647 AVX512ER :{EVEX} VRSQRT28PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2648 AVX512ER :{EVEX} VRSQRT28SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2649 AVX512ER :{EVEX} VRSQRT28PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2650 AVX512ER :{EVEX} VEXP2PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2651 AVX512ER :{EVEX} VEXP2PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2652 AVX512F :{EVEX} VMINSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2653 AVX512VL :{EVEX} VMINPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2654 AVX512VL :{EVEX} VMINPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2655 AVX512F :{EVEX} VMINPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2656 AVX512F :{EVEX} VMINSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2657 AVX512VL :{EVEX} VMINPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2658 AVX512VL :{EVEX} VMINPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2659 AVX512F :{EVEX} VMINPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2660 AVX512F :{EVEX} VMAXSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2661 AVX512VL :{EVEX} VMAXPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2662 AVX512VL :{EVEX} VMAXPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2663 AVX512F :{EVEX} VMAXPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2664 AVX512F :{EVEX} VMAXSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2665 AVX512VL :{EVEX} VMAXPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2666 AVX512VL :{EVEX} VMAXPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2667 AVX512F :{EVEX} VMAXPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2668 AVX512F :{EVEX} VCMPSS k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2669 AVX512VL :{EVEX} VCMPPS k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2670 AVX512VL :{EVEX} VCMPPS k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2671 AVX512F :{EVEX} VCMPPS k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2672 AVX512F :{EVEX} VCMPSD k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2673 AVX512VL :{EVEX} VCMPPD k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2674 AVX512VL :{EVEX} VCMPPD k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2675 AVX512F :{EVEX} VCMPPD k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2676 AVX512F :{EVEX} VCOMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 2677 AVX512F :{EVEX} VUCOMISS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 2678 AVX512F :{EVEX} VCOMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 2679 AVX512F :{EVEX} VUCOMISD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 2680 AVX512VLDQ :{EVEX} VANDPS xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2681 AVX512VLDQ :{EVEX} VANDPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2682 AVX512VLDQ :{EVEX} VANDPS ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2683 AVX512VLDQ :{EVEX} VANDPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2684 AVX512DQ :{EVEX} VANDPS zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2685 AVX512DQ :{EVEX} VANDPS zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2686 AVX512VLDQ :{EVEX} VANDPD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2687 AVX512VLDQ :{EVEX} VANDPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2688 AVX512VLDQ :{EVEX} VANDPD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2689 AVX512VLDQ :{EVEX} VANDPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2690 AVX512DQ :{EVEX} VANDPD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2691 AVX512DQ :{EVEX} VANDPD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2692 AVX512VLDQ :{EVEX} VANDNPS xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2693 AVX512VLDQ :{EVEX} VANDNPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2694 AVX512VLDQ :{EVEX} VANDNPS ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2695 AVX512VLDQ :{EVEX} VANDNPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2696 AVX512DQ :{EVEX} VANDNPS zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2697 AVX512DQ :{EVEX} VANDNPS zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2698 AVX512VLDQ :{EVEX} VANDNPD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2699 AVX512VLDQ :{EVEX} VANDNPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2700 AVX512VLDQ :{EVEX} VANDNPD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2701 AVX512VLDQ :{EVEX} VANDNPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2702 AVX512DQ :{EVEX} VANDNPD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2703 AVX512DQ :{EVEX} VANDNPD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2704 AVX512VLDQ :{EVEX} VORPS xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2705 AVX512VLDQ :{EVEX} VORPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2706 AVX512VLDQ :{EVEX} VORPS ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2707 AVX512VLDQ :{EVEX} VORPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2708 AVX512DQ :{EVEX} VORPS zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2709 AVX512DQ :{EVEX} VORPS zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2710 AVX512VLDQ :{EVEX} VORPD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2711 AVX512VLDQ :{EVEX} VORPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2712 AVX512VLDQ :{EVEX} VORPD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2713 AVX512VLDQ :{EVEX} VORPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2714 AVX512DQ :{EVEX} VORPD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2715 AVX512DQ :{EVEX} VORPD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2716 AVX512VLDQ :{EVEX} VXORPS xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2717 AVX512VLDQ :{EVEX} VXORPS xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2718 AVX512VLDQ :{EVEX} VXORPS ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2719 AVX512VLDQ :{EVEX} VXORPS ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2720 AVX512DQ :{EVEX} VXORPS zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2721 AVX512DQ :{EVEX} VXORPS zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2722 AVX512VLDQ :{EVEX} VXORPD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2723 AVX512VLDQ :{EVEX} VXORPD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2724 AVX512VLDQ :{EVEX} VXORPD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2725 AVX512VLDQ :{EVEX} VXORPD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2726 AVX512DQ :{EVEX} VXORPD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2727 AVX512DQ :{EVEX} VXORPD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2728 AVX512VL :{EVEX} VCVTPS2PH xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2729 AVX512VL :{EVEX} VCVTPS2PH xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2730 AVX512F :{EVEX} VCVTPS2PH ymm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2731 AVX512VL :{EVEX} VCVTPH2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2732 AVX512VL :{EVEX} VCVTPH2PS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2733 AVX512F :{EVEX} VCVTPH2PS zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2734 AVX512VL :{EVEX} VCVTPS2PH + VCVTPH2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2735 AVX512VL :{EVEX} VCVTPS2PH + VCVTPH2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2736 AVX512F :{EVEX} VCVTPS2PH + VCVTPH2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2737 AVX512F :{EVEX} VCVTSS2SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2738 AVX512VL :{EVEX} VCVTPS2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2739 AVX512VL :{EVEX} VCVTPS2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2740 AVX512F :{EVEX} VCVTPS2PD zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2741 AVX512F :{EVEX} VCVTSD2SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2742 AVX512VL :{EVEX} VCVTPD2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2743 AVX512VL :{EVEX} VCVTPD2PS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2744 AVX512F :{EVEX} VCVTPD2PS ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2745 AVX512F :{EVEX} VCVTSD2SS + VCVTSD2SS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2746 AVX512VL :{EVEX} VCVTPD2PS + VCVTPD2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2747 AVX512VL :{EVEX} VCVTPD2PS + VCVTPD2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2748 AVX512F :{EVEX} VCVTPD2PS + VCVTPD2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2749 AVX512F :{EVEX} VCVTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2750 AVX512F_X64 :{EVEX} VCVTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2751 AVX512F :{EVEX} VCVTSS2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2752 AVX512F_X64 :{EVEX} VCVTSS2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2753 AVX512F :{EVEX} VCVTTSS2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2754 AVX512F_X64 :{EVEX} VCVTTSS2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2755 AVX512F :{EVEX} VCVTTSS2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2756 AVX512F_X64 :{EVEX} VCVTTSS2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2757 AVX512F :{EVEX} VCVTSI2SS xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2758 AVX512F_X64 :{EVEX} VCVTSI2SS xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 2759 AVX512F :{EVEX} VCVTUSI2SS xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2760 AVX512F_X64 :{EVEX} VCVTUSI2SS xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 2761 AVX512F :{EVEX} VCVTSS2SI + VCVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2762 AVX512F_X64 :{EVEX} VCVTSS2SI + VCVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2763 AVX512F :{EVEX} VCVTSS2USI + VCVTUSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2764 AVX512F_X64 :{EVEX} VCVTSS2USI + VCVTUSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2765 AVX512F :{EVEX} VCVTTSS2SI + VCVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2766 AVX512F_X64 :{EVEX} VCVTTSS2SI + VCVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2767 AVX512F :{EVEX} VCVTTSS2USI + VCVTUSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2768 AVX512F_X64 :{EVEX} VCVTTSS2USI + VCVTUSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2769 AVX512F :{EVEX} VCVTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2770 AVX512F_X64 :{EVEX} VCVTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2771 AVX512F :{EVEX} VCVTSD2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2772 AVX512F_X64 :{EVEX} VCVTSD2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2773 AVX512F :{EVEX} VCVTTSD2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2774 AVX512F_X64 :{EVEX} VCVTTSD2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2775 AVX512F :{EVEX} VCVTTSD2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2776 AVX512F_X64 :{EVEX} VCVTTSD2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 2777 AVX512F :{EVEX} VCVTSI2SD xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2778 AVX512F_X64 :{EVEX} VCVTSI2SD xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 2779 AVX512F :{EVEX} VCVTUSI2SD xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 2780 AVX512F_X64 :{EVEX} VCVTUSI2SD xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 2781 AVX512F :{EVEX} VCVTSD2SI + VCVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2782 AVX512F_X64 :{EVEX} VCVTSD2SI + VCVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2783 AVX512F :{EVEX} VCVTSD2USI + VCVTUSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2784 AVX512F_X64 :{EVEX} VCVTSD2USI + VCVTUSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2785 AVX512F :{EVEX} VCVTTSD2SI + VCVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2786 AVX512F_X64 :{EVEX} VCVTTSD2SI + VCVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2787 AVX512F :{EVEX} VCVTTSD2USI + VCVTUSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2788 AVX512F_X64 :{EVEX} VCVTTSD2USI + VCVTUSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2789 AVX512VL :{EVEX} VCVTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2790 AVX512VL :{EVEX} VCVTPS2DQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2791 AVX512F :{EVEX} VCVTPS2DQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2792 AVX512VL :{EVEX} VCVTPS2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2793 AVX512VL :{EVEX} VCVTPS2UDQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2794 AVX512F :{EVEX} VCVTPS2UDQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2795 AVX512VLDQ :{EVEX} VCVTPS2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2796 AVX512VLDQ :{EVEX} VCVTPS2QQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2797 AVX512DQ :{EVEX} VCVTPS2QQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2798 AVX512VLDQ :{EVEX} VCVTPS2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2799 AVX512VLDQ :{EVEX} VCVTPS2UQQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2800 AVX512DQ :{EVEX} VCVTPS2UQQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2801 AVX512VL :{EVEX} VCVTTPS2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2802 AVX512VL :{EVEX} VCVTTPS2DQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2803 AVX512F :{EVEX} VCVTTPS2DQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2804 AVX512VL :{EVEX} VCVTTPS2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2805 AVX512VL :{EVEX} VCVTTPS2UDQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2806 AVX512F :{EVEX} VCVTTPS2UDQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2807 AVX512VLDQ :{EVEX} VCVTTPS2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2808 AVX512VLDQ :{EVEX} VCVTTPS2QQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2809 AVX512DQ :{EVEX} VCVTTPS2QQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2810 AVX512VLDQ :{EVEX} VCVTTPS2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2811 AVX512VLDQ :{EVEX} VCVTTPS2UQQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2812 AVX512DQ :{EVEX} VCVTTPS2UQQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2813 AVX512VL :{EVEX} VCVTDQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2814 AVX512VL :{EVEX} VCVTDQ2PS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2815 AVX512F :{EVEX} VCVTDQ2PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2816 AVX512VL :{EVEX} VCVTUDQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2817 AVX512VL :{EVEX} VCVTUDQ2PS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2818 AVX512F :{EVEX} VCVTUDQ2PS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2819 AVX512VLDQ :{EVEX} VCVTQQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2820 AVX512VLDQ :{EVEX} VCVTQQ2PS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2821 AVX512DQ :{EVEX} VCVTQQ2PS ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2822 AVX512VLDQ :{EVEX} VCVTUQQ2PS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2823 AVX512VLDQ :{EVEX} VCVTUQQ2PS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2824 AVX512DQ :{EVEX} VCVTUQQ2PS ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2825 AVX512VL :{EVEX} VCVTPS2DQ + VCVTDQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2826 AVX512VL :{EVEX} VCVTPS2DQ + VCVTDQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2827 AVX512F :{EVEX} VCVTPS2DQ + VCVTDQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2828 AVX512VL :{EVEX} VCVTPS2UDQ + VCVTUDQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2829 AVX512VL :{EVEX} VCVTPS2UDQ + VCVTUDQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2830 AVX512F :{EVEX} VCVTPS2UDQ + VCVTUDQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2831 AVX512VLDQ :{EVEX} VCVTPS2QQ + VCVTQQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2832 AVX512VLDQ :{EVEX} VCVTPS2QQ + VCVTQQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2833 AVX512DQ :{EVEX} VCVTPS2QQ + VCVTQQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2834 AVX512VLDQ :{EVEX} VCVTPS2UQQ + VCVTUQQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2835 AVX512VLDQ :{EVEX} VCVTPS2UQQ + VCVTUQQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2836 AVX512DQ :{EVEX} VCVTPS2UQQ + VCVTUQQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2837 AVX512VL :{EVEX} VCVTTPS2DQ + VCVTDQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2838 AVX512VL :{EVEX} VCVTTPS2DQ + VCVTDQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2839 AVX512F :{EVEX} VCVTTPS2DQ + VCVTDQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2840 AVX512VL :{EVEX} VCVTTPS2UDQ + VCVTUDQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2841 AVX512VL :{EVEX} VCVTTPS2UDQ + VCVTUDQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2842 AVX512F :{EVEX} VCVTTPS2UDQ + VCVTUDQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2843 AVX512VLDQ :{EVEX} VCVTTPS2QQ + VCVTQQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2844 AVX512VLDQ :{EVEX} VCVTTPS2QQ + VCVTQQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2845 AVX512DQ :{EVEX} VCVTTPS2QQ + VCVTQQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2846 AVX512VLDQ :{EVEX} VCVTTPS2UQQ + VCVTUQQ2PS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2847 AVX512VLDQ :{EVEX} VCVTTPS2UQQ + VCVTUQQ2PS ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2848 AVX512DQ :{EVEX} VCVTTPS2UQQ + VCVTUQQ2PS zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2849 AVX512VL :{EVEX} VCVTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2850 AVX512VL :{EVEX} VCVTPD2DQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2851 AVX512F :{EVEX} VCVTPD2DQ ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2852 AVX512VL :{EVEX} VCVTPD2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2853 AVX512VL :{EVEX} VCVTPD2UDQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2854 AVX512F :{EVEX} VCVTPD2UDQ ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2855 AVX512VLDQ :{EVEX} VCVTPD2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2856 AVX512VLDQ :{EVEX} VCVTPD2QQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2857 AVX512DQ :{EVEX} VCVTPD2QQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2858 AVX512VLDQ :{EVEX} VCVTPD2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2859 AVX512VLDQ :{EVEX} VCVTPD2UQQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2860 AVX512DQ :{EVEX} VCVTPD2UQQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2861 AVX512VL :{EVEX} VCVTTPD2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2862 AVX512VL :{EVEX} VCVTTPD2DQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2863 AVX512F :{EVEX} VCVTTPD2DQ ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2864 AVX512VL :{EVEX} VCVTTPD2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2865 AVX512VL :{EVEX} VCVTTPD2UDQ xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2866 AVX512F :{EVEX} VCVTTPD2UDQ ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2867 AVX512VLDQ :{EVEX} VCVTTPD2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2868 AVX512VLDQ :{EVEX} VCVTTPD2QQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2869 AVX512DQ :{EVEX} VCVTTPD2QQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2870 AVX512VLDQ :{EVEX} VCVTTPD2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2871 AVX512VLDQ :{EVEX} VCVTTPD2UQQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2872 AVX512DQ :{EVEX} VCVTTPD2UQQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2873 AVX512VL :{EVEX} VCVTDQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2874 AVX512VL :{EVEX} VCVTDQ2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2875 AVX512F :{EVEX} VCVTDQ2PD zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2876 AVX512VL :{EVEX} VCVTUDQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2877 AVX512VL :{EVEX} VCVTUDQ2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2878 AVX512F :{EVEX} VCVTUDQ2PD zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2879 AVX512VLDQ :{EVEX} VCVTQQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2880 AVX512VLDQ :{EVEX} VCVTQQ2PD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2881 AVX512DQ :{EVEX} VCVTQQ2PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2882 AVX512VLDQ :{EVEX} VCVTUQQ2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2883 AVX512VLDQ :{EVEX} VCVTUQQ2PD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2884 AVX512DQ :{EVEX} VCVTUQQ2PD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2885 AVX512VL :{EVEX} VCVTPD2DQ + VCVTDQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2886 AVX512VL :{EVEX} VCVTPD2DQ + VCVTDQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2887 AVX512F :{EVEX} VCVTPD2DQ + VCVTDQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2888 AVX512VL :{EVEX} VCVTPD2UDQ + VCVTUDQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2889 AVX512VL :{EVEX} VCVTPD2UDQ + VCVTUDQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2890 AVX512F :{EVEX} VCVTPD2UDQ + VCVTUDQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2891 AVX512VLDQ :{EVEX} VCVTPD2QQ + VCVTQQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2892 AVX512VLDQ :{EVEX} VCVTPD2QQ + VCVTQQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2893 AVX512DQ :{EVEX} VCVTPD2QQ + VCVTQQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2894 AVX512VLDQ :{EVEX} VCVTPD2UQQ + VCVTUQQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2895 AVX512VLDQ :{EVEX} VCVTPD2UQQ + VCVTUQQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2896 AVX512DQ :{EVEX} VCVTPD2UQQ + VCVTUQQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2897 AVX512VL :{EVEX} VCVTTPD2DQ + VCVTDQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2898 AVX512VL :{EVEX} VCVTTPD2DQ + VCVTDQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2899 AVX512F :{EVEX} VCVTTPD2DQ + VCVTDQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2900 AVX512VL :{EVEX} VCVTTPD2UDQ + VCVTUDQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2901 AVX512VL :{EVEX} VCVTTPD2UDQ + VCVTUDQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2902 AVX512F :{EVEX} VCVTTPD2UDQ + VCVTUDQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2903 AVX512VLDQ :{EVEX} VCVTTPD2QQ + VCVTQQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2904 AVX512VLDQ :{EVEX} VCVTTPD2QQ + VCVTQQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2905 AVX512DQ :{EVEX} VCVTTPD2QQ + VCVTQQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2906 AVX512VLDQ :{EVEX} VCVTTPD2UQQ + VCVTUQQ2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2907 AVX512VLDQ :{EVEX} VCVTTPD2UQQ + VCVTUQQ2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2908 AVX512DQ :{EVEX} VCVTTPD2UQQ + VCVTUQQ2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2909 AVX512VL :{EVEX} VBLENDMPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2910 AVX512VL :{EVEX} VBLENDMPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2911 AVX512F :{EVEX} VBLENDMPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2912 AVX512VL :{EVEX} VBLENDMPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2913 AVX512VL :{EVEX} VBLENDMPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2914 AVX512F :{EVEX} VBLENDMPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2915 AVX512DQ :{EVEX} VFPCLASSSS k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2916 AVX512VLDQ :{EVEX} VFPCLASSPS k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2917 AVX512VLDQ :{EVEX} VFPCLASSPS k, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2918 AVX512DQ :{EVEX} VFPCLASSPS k, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2919 AVX512DQ :{EVEX} VFPCLASSSD k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2920 AVX512VLDQ :{EVEX} VFPCLASSPD k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2921 AVX512VLDQ :{EVEX} VFPCLASSPD k, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2922 AVX512DQ :{EVEX} VFPCLASSPD k, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 2923 AVX512VL :{EVEX} VCOMPRESSPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2924 AVX512VL :{EVEX} VCOMPRESSPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2925 AVX512F :{EVEX} VCOMPRESSPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2926 AVX512VL :{EVEX} VCOMPRESSPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2927 AVX512VL :{EVEX} VCOMPRESSPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2928 AVX512F :{EVEX} VCOMPRESSPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2929 AVX512VL :{EVEX} VCOMPRESSPS xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2930 AVX512VL :{EVEX} VCOMPRESSPS ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2931 AVX512F :{EVEX} VCOMPRESSPS zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2932 AVX512VL :{EVEX} VCOMPRESSPD xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2933 AVX512VL :{EVEX} VCOMPRESSPD ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2934 AVX512F :{EVEX} VCOMPRESSPD zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2935 AVX512VL :{EVEX} VEXPANDPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2936 AVX512VL :{EVEX} VEXPANDPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2937 AVX512F :{EVEX} VEXPANDPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2938 AVX512VL :{EVEX} VEXPANDPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2939 AVX512VL :{EVEX} VEXPANDPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2940 AVX512F :{EVEX} VEXPANDPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2941 AVX512VL :{EVEX} VEXPANDPS xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2942 AVX512VL :{EVEX} VEXPANDPS ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2943 AVX512F :{EVEX} VEXPANDPS zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2944 AVX512VL :{EVEX} VEXPANDPD xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2945 AVX512VL :{EVEX} VEXPANDPD ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2946 AVX512F :{EVEX} VEXPANDPD zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2947 AVX512F :{EVEX} VFIXUPIMMSS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2948 AVX512VL :{EVEX} VFIXUPIMMPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2949 AVX512VL :{EVEX} VFIXUPIMMPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2950 AVX512F :{EVEX} VFIXUPIMMPS zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2951 AVX512F :{EVEX} VFIXUPIMMSD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2952 AVX512VL :{EVEX} VFIXUPIMMPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2953 AVX512VL :{EVEX} VFIXUPIMMPD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2954 AVX512F :{EVEX} VFIXUPIMMPD zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2955 AVX512F :{EVEX} VGETEXPSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2956 AVX512VL :{EVEX} VGETEXPPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2957 AVX512VL :{EVEX} VGETEXPPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2958 AVX512F :{EVEX} VGETEXPPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2959 AVX512F :{EVEX} VGETEXPSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2960 AVX512VL :{EVEX} VGETEXPPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2961 AVX512VL :{EVEX} VGETEXPPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2962 AVX512F :{EVEX} VGETEXPPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2963 AVX512F :{EVEX} VGETMANTSS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2964 AVX512VL :{EVEX} VGETMANTPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2965 AVX512VL :{EVEX} VGETMANTPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2966 AVX512F :{EVEX} VGETMANTPS zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2967 AVX512F :{EVEX} VGETMANTSD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2968 AVX512VL :{EVEX} VGETMANTPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2969 AVX512VL :{EVEX} VGETMANTPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2970 AVX512F :{EVEX} VGETMANTPD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2971 AVX512DQ :{EVEX} VRANGESS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2972 AVX512VLDQ :{EVEX} VRANGEPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2973 AVX512VLDQ :{EVEX} VRANGEPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2974 AVX512DQ :{EVEX} VRANGEPS zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2975 AVX512DQ :{EVEX} VRANGESD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2976 AVX512VLDQ :{EVEX} VRANGEPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2977 AVX512VLDQ :{EVEX} VRANGEPD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2978 AVX512DQ :{EVEX} VRANGEPD zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2979 AVX512DQ :{EVEX} VREDUCESS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2980 AVX512VLDQ :{EVEX} VREDUCEPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2981 AVX512VLDQ :{EVEX} VREDUCEPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2982 AVX512DQ :{EVEX} VREDUCEPS zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2983 AVX512DQ :{EVEX} VREDUCESD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2984 AVX512VLDQ :{EVEX} VREDUCEPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2985 AVX512VLDQ :{EVEX} VREDUCEPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2986 AVX512DQ :{EVEX} VREDUCEPD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2987 AVX512F :{EVEX} VRNDSCALESS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2988 AVX512VL :{EVEX} VRNDSCALEPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2989 AVX512VL :{EVEX} VRNDSCALEPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2990 AVX512F :{EVEX} VRNDSCALEPS zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2991 AVX512F :{EVEX} VRNDSCALESD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2992 AVX512VL :{EVEX} VRNDSCALEPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2993 AVX512VL :{EVEX} VRNDSCALEPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2994 AVX512F :{EVEX} VRNDSCALEPD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2995 AVX512F :{EVEX} VSCALEFSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2996 AVX512VL :{EVEX} VSCALEFPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2997 AVX512VL :{EVEX} VSCALEFPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2998 AVX512F :{EVEX} VSCALEFPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 2999 AVX512F :{EVEX} VSCALEFSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3000 AVX512VL :{EVEX} VSCALEFPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3001 AVX512VL :{EVEX} VSCALEFPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3002 AVX512F :{EVEX} VSCALEFPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3003 AVX512F :{EVEX} VMOVSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3004 AVX512F :{EVEX} VMOVSS xmm1, xmm2, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3005 AVX512F :{EVEX} VMOVSS xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 3006 AVX512F :{EVEX} VMOVSS [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 3007 AVX512F :{EVEX} VMOVSS LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3008 AVX512F :{EVEX} VMOVLHPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3009 AVX512F :{EVEX} VMOVLHPS xmm1, xmm2, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3010 AVX512F :{EVEX} VMOVHLPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3011 AVX512F :{EVEX} VMOVHLPS xmm1, xmm2, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3012 AVX512F :{EVEX} VMOVLPS xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3013 AVX512F :{EVEX} VMOVLPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3014 AVX512F :{EVEX} VMOVHPS xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3015 AVX512F :{EVEX} VMOVHPS [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3016 AVX512VL :{EVEX} VMOVAPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3017 AVX512VL :{EVEX} VMOVAPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3018 AVX512VL :{EVEX} VMOVAPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3019 AVX512VL :{EVEX} VMOVAPS ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3020 AVX512F :{EVEX} VMOVAPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3021 AVX512F :{EVEX} VMOVAPS zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3022 AVX512VL :{EVEX} VMOVAPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3023 AVX512VL :{EVEX} VMOVAPS ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3024 AVX512F :{EVEX} VMOVAPS zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3025 AVX512VL :{EVEX} VMOVAPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3026 AVX512VL :{EVEX} VMOVAPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3027 AVX512F :{EVEX} VMOVAPS [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3028 AVX512VL :{EVEX} VMOVAPS xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3029 AVX512VL :{EVEX} VMOVAPS ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3030 AVX512F :{EVEX} VMOVAPS zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3031 AVX512VL :{EVEX} VMOVUPS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3032 AVX512VL :{EVEX} VMOVUPS xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3033 AVX512VL :{EVEX} VMOVUPS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3034 AVX512VL :{EVEX} VMOVUPS ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3035 AVX512F :{EVEX} VMOVUPS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3036 AVX512F :{EVEX} VMOVUPS zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3037 AVX512VL :{EVEX} VMOVUPS xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3038 AVX512VL :{EVEX} VMOVUPS ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3039 AVX512F :{EVEX} VMOVUPS zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3040 AVX512VL :{EVEX} VMOVUPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3041 AVX512VL :{EVEX} VMOVUPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3042 AVX512F :{EVEX} VMOVUPS [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3043 AVX512VL :{EVEX} VMOVUPS xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3044 AVX512VL :{EVEX} VMOVUPS ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3045 AVX512F :{EVEX} VMOVUPS zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3046 AVX512VL :{EVEX} VMOVUPS xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3047 AVX512VL :{EVEX} VMOVUPS ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3048 AVX512F :{EVEX} VMOVUPS zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3049 AVX512VL :{EVEX} VMOVUPS [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3050 AVX512VL :{EVEX} VMOVUPS [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3051 AVX512F :{EVEX} VMOVUPS [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3052 AVX512VL :{EVEX} VMOVUPS xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3053 AVX512VL :{EVEX} VMOVUPS ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3054 AVX512F :{EVEX} VMOVUPS zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3055 AVX512VL :{EVEX} VMOVNTPS [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3056 AVX512VL :{EVEX} VMOVNTPS [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3057 AVX512F :{EVEX} VMOVNTPS [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3058 AVX512VL :{EVEX} VMOVSLDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3059 AVX512VL :{EVEX} VMOVSLDUP ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3060 AVX512F :{EVEX} VMOVSLDUP zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3061 AVX512VL :{EVEX} VMOVSHDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3062 AVX512VL :{EVEX} VMOVSHDUP ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3063 AVX512F :{EVEX} VMOVSHDUP zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3064 AVX512F :{EVEX} VMOVSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3065 AVX512F :{EVEX} VMOVSD xmm1, xmm2, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3066 AVX512F :{EVEX} VMOVSD xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3067 AVX512F :{EVEX} VMOVSD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3068 AVX512F :{EVEX} VMOVSD LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3069 AVX512F :{EVEX} VMOVLPD xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3070 AVX512F :{EVEX} VMOVLPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3071 AVX512F :{EVEX} VMOVHPD xmm, xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3072 AVX512F :{EVEX} VMOVHPD [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3073 AVX512VL :{EVEX} VMOVAPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3074 AVX512VL :{EVEX} VMOVAPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3075 AVX512VL :{EVEX} VMOVAPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3076 AVX512VL :{EVEX} VMOVAPD ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3077 AVX512F :{EVEX} VMOVAPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3078 AVX512F :{EVEX} VMOVAPD zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3079 AVX512VL :{EVEX} VMOVAPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3080 AVX512VL :{EVEX} VMOVAPD ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3081 AVX512F :{EVEX} VMOVAPD zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3082 AVX512VL :{EVEX} VMOVAPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3083 AVX512VL :{EVEX} VMOVAPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3084 AVX512F :{EVEX} VMOVAPD [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3085 AVX512VL :{EVEX} VMOVAPD xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3086 AVX512VL :{EVEX} VMOVAPD ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3087 AVX512F :{EVEX} VMOVAPD zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3088 AVX512VL :{EVEX} VMOVUPD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3089 AVX512VL :{EVEX} VMOVUPD xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3090 AVX512VL :{EVEX} VMOVUPD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3091 AVX512VL :{EVEX} VMOVUPD ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3092 AVX512F :{EVEX} VMOVUPD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3093 AVX512F :{EVEX} VMOVUPD zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3094 AVX512VL :{EVEX} VMOVUPD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3095 AVX512VL :{EVEX} VMOVUPD ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3096 AVX512F :{EVEX} VMOVUPD zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3097 AVX512VL :{EVEX} VMOVUPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3098 AVX512VL :{EVEX} VMOVUPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3099 AVX512F :{EVEX} VMOVUPD [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3100 AVX512VL :{EVEX} VMOVUPD xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3101 AVX512VL :{EVEX} VMOVUPD ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3102 AVX512F :{EVEX} VMOVUPD zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3103 AVX512VL :{EVEX} VMOVUPD xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3104 AVX512VL :{EVEX} VMOVUPD ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3105 AVX512F :{EVEX} VMOVUPD zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3106 AVX512VL :{EVEX} VMOVUPD [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3107 AVX512VL :{EVEX} VMOVUPD [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3108 AVX512F :{EVEX} VMOVUPD [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3109 AVX512VL :{EVEX} VMOVUPD xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3110 AVX512VL :{EVEX} VMOVUPD ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3111 AVX512F :{EVEX} VMOVUPD zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3112 AVX512VL :{EVEX} VMOVNTPD [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3113 AVX512VL :{EVEX} VMOVNTPD [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3114 AVX512F :{EVEX} VMOVNTPD [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3115 AVX512VL :{EVEX} VMOVDDUP xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3116 AVX512VL :{EVEX} VMOVDDUP ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3117 AVX512F :{EVEX} VMOVDDUP zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3118 AVX512VL :{EVEX} VBROADCASTSS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3119 AVX512VL :{EVEX} VBROADCASTSS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3120 AVX512F :{EVEX} VBROADCASTSS zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3121 AVX512VL :{EVEX} VBROADCASTSS xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 3122 AVX512VL :{EVEX} VBROADCASTSS ymm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 3123 AVX512F :{EVEX} VBROADCASTSS zmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 3124 AVX512VLDQ :{EVEX} VBROADCASTF32X2 ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3125 AVX512DQ :{EVEX} VBROADCASTF32X2 zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3126 AVX512VLDQ :{EVEX} VBROADCASTF32X2 ymm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3127 AVX512DQ :{EVEX} VBROADCASTF32X2 zmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3128 AVX512VL :{EVEX} VBROADCASTF32X4 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3129 AVX512F :{EVEX} VBROADCASTF32X4 zmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3130 AVX512DQ :{EVEX} VBROADCASTF32X8 zmm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3131 AVX512VL :{EVEX} VBROADCASTSD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3132 AVX512F :{EVEX} VBROADCASTSD zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3133 AVX512VL :{EVEX} VBROADCASTSD ymm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3134 AVX512F :{EVEX} VBROADCASTSD zmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3135 AVX512VLDQ :{EVEX} VBROADCASTF64X2 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3136 AVX512DQ :{EVEX} VBROADCASTF64X2 zmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3137 AVX512F :{EVEX} VBROADCASTF64X4 zmm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3138 AVX512F :{EVEX} VEXTRACTPS r32, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3139 AVX512F :{EVEX} VEXTRACTPS [m32], xmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3140 AVX512VL :{EVEX} VEXTRACTF32X4 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3141 AVX512F :{EVEX} VEXTRACTF32X4 xmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3142 AVX512VL :{EVEX} VEXTRACTF32X4 [m128], ymm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3143 AVX512F :{EVEX} VEXTRACTF32X4 [m128], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3144 AVX512DQ :{EVEX} VEXTRACTF32X8 ymm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3145 AVX512DQ :{EVEX} VEXTRACTF32X8 [m256], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3146 AVX512VLDQ :{EVEX} VEXTRACTF64X2 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3147 AVX512DQ :{EVEX} VEXTRACTF64X2 xmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3148 AVX512VLDQ :{EVEX} VEXTRACTF64X2 [m128], ymm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3149 AVX512DQ :{EVEX} VEXTRACTF64X2 [m128], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3150 AVX512F :{EVEX} VEXTRACTF64X4 ymm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3151 AVX512F :{EVEX} VEXTRACTF64X4 [m256], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 3152 AVX512F :{EVEX} VINSERTPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3153 AVX512F :{EVEX} VINSERTPS xmm, xmm, [m32], im8 L: [memory dep.] T: 0.00ns= 0.000c 3154 AVX512VL :{EVEX} VINSERTF32X4 ymm, ymm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3155 AVX512F :{EVEX} VINSERTF32X4 zmm, zmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3156 AVX512VL :{EVEX} VINSERTF32X4 ymm, ymm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3157 AVX512F :{EVEX} VINSERTF32X4 zmm, zmm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3158 AVX512DQ :{EVEX} VINSERTF32X8 zmm, zmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3159 AVX512DQ :{EVEX} VINSERTF32X8 zmm, zmm, [m256], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3160 AVX512VLDQ :{EVEX} VINSERTF64X2 ymm, ymm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3161 AVX512DQ :{EVEX} VINSERTF64X2 zmm, zmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3162 AVX512VLDQ :{EVEX} VINSERTF64X2 ymm, ymm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3163 AVX512DQ :{EVEX} VINSERTF64X2 zmm, zmm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3164 AVX512F :{EVEX} VINSERTF64X4 zmm, zmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3165 AVX512F :{EVEX} VINSERTF64X4 zmm, zmm, [m256], imm8 L: [memory dep.] T: 0.00ns= 0.000c 3166 AVX512VL :{EVEX} VUNPCKLPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3167 AVX512VL :{EVEX} VUNPCKLPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3168 AVX512F :{EVEX} VUNPCKLPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3169 AVX512VL :{EVEX} VUNPCKHPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3170 AVX512VL :{EVEX} VUNPCKHPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3171 AVX512F :{EVEX} VUNPCKHPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3172 AVX512VL :{EVEX} VUNPCKLPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3173 AVX512VL :{EVEX} VUNPCKLPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3174 AVX512F :{EVEX} VUNPCKLPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3175 AVX512VL :{EVEX} VUNPCKHPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3176 AVX512VL :{EVEX} VUNPCKHPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3177 AVX512F :{EVEX} VUNPCKHPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3178 AVX512VL :{EVEX} VSHUFPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3179 AVX512VL :{EVEX} VSHUFPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3180 AVX512F :{EVEX} VSHUFPS zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3181 AVX512VL :{EVEX} VSHUFPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3182 AVX512VL :{EVEX} VSHUFPD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3183 AVX512F :{EVEX} VSHUFPD zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3184 AVX512VL :{EVEX} VSHUFF32X4 ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3185 AVX512F :{EVEX} VSHUFF32X4 zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3186 AVX512VL :{EVEX} VSHUFF64X2 ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3187 AVX512F :{EVEX} VSHUFF64X2 zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3188 AVX512VL :{EVEX} VPERMPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3189 AVX512F :{EVEX} VPERMPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3190 AVX512VL :{EVEX} VPERMPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3191 AVX512F :{EVEX} VPERMPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3192 AVX512VL :{EVEX} VPERMPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3193 AVX512F :{EVEX} VPERMPD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3194 AVX512VL :{EVEX} VPERMILPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3195 AVX512VL :{EVEX} VPERMILPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3196 AVX512F :{EVEX} VPERMILPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3197 AVX512VL :{EVEX} VPERMILPS xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3198 AVX512VL :{EVEX} VPERMILPS ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3199 AVX512F :{EVEX} VPERMILPS zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3200 AVX512VL :{EVEX} VPERMI2PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3201 AVX512VL :{EVEX} VPERMI2PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3202 AVX512F :{EVEX} VPERMI2PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3203 AVX512VL :{EVEX} VPERMT2PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3204 AVX512VL :{EVEX} VPERMT2PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3205 AVX512F :{EVEX} VPERMT2PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3206 AVX512VL :{EVEX} VPERMILPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3207 AVX512VL :{EVEX} VPERMILPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3208 AVX512F :{EVEX} VPERMILPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3209 AVX512VL :{EVEX} VPERMILPD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3210 AVX512VL :{EVEX} VPERMILPD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3211 AVX512F :{EVEX} VPERMILPD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3212 AVX512VL :{EVEX} VPERMI2PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3213 AVX512VL :{EVEX} VPERMI2PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3214 AVX512F :{EVEX} VPERMI2PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3215 AVX512VL :{EVEX} VPERMT2PD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3216 AVX512VL :{EVEX} VPERMT2PD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3217 AVX512F :{EVEX} VPERMT2PD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3218 AVX512PF :{EVEX} VGATHERPF0DPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3219 AVX512PF :{EVEX} VGATHERPF0QPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3220 AVX512PF :{EVEX} VGATHERPF0DPD [ym64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3221 AVX512PF :{EVEX} VGATHERPF0QPD [zm64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3222 AVX512PF :{EVEX} VGATHERPF1DPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3223 AVX512PF :{EVEX} VGATHERPF1QPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3224 AVX512PF :{EVEX} VGATHERPF1DPD [ym64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3225 AVX512PF :{EVEX} VGATHERPF1QPD [zm64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3226 AVX512PF :{EVEX} VSCATTERPF0DPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3227 AVX512PF :{EVEX} VSCATTERPF0QPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3228 AVX512PF :{EVEX} VSCATTERPF0DPD [ym64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3229 AVX512PF :{EVEX} VSCATTERPF0QPD [zm64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3230 AVX512PF :{EVEX} VSCATTERPF1DPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3231 AVX512PF :{EVEX} VSCATTERPF1QPS [zm32]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3232 AVX512PF :{EVEX} VSCATTERPF1DPD [ym64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3233 AVX512PF :{EVEX} VSCATTERPF1QPD [zm64]{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3234 AVX512VL :{EVEX} VGATHERDPS xmm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3235 AVX512VL :{EVEX} VGATHERDPS ymm {k}, [ym32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3236 AVX512F :{EVEX} VGATHERDPS zmm {k}, [zm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3237 AVX512VL :{EVEX} VGATHERQPS xmm {k}, [xm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3238 AVX512VL :{EVEX} VGATHERQPS xmm {k}, [ym64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3239 AVX512F :{EVEX} VGATHERQPS ymm {k}, [zm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3240 AVX512VL :{EVEX} VGATHERDPD xmm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3241 AVX512VL :{EVEX} VGATHERDPD ymm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3242 AVX512F :{EVEX} VGATHERDPD zmm {k}, [ym32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3243 AVX512VL :{EVEX} VGATHERQPD xmm {k}, [xm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3244 AVX512VL :{EVEX} VGATHERQPD ymm {k}, [ym64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3245 AVX512F :{EVEX} VGATHERQPD zmm {k}, [zm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3246 AVX512VL :{EVEX} VSCATTERDPS [xm32] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3247 AVX512VL :{EVEX} VSCATTERDPS [ym32] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3248 AVX512F :{EVEX} VSCATTERDPS [zm32] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3249 AVX512VL :{EVEX} VSCATTERQPS [xm64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3250 AVX512VL :{EVEX} VSCATTERQPS [ym64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3251 AVX512F :{EVEX} VSCATTERQPS [zm64] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3252 AVX512VL :{EVEX} VSCATTERDPD [xm32] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3253 AVX512VL :{EVEX} VSCATTERDPD [xm32] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3254 AVX512F :{EVEX} VSCATTERDPD [ym32] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3255 AVX512VL :{EVEX} VSCATTERQPD [xm64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3256 AVX512VL :{EVEX} VSCATTERQPD [ym64] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3257 AVX512F :{EVEX} VSCATTERQPD [zm64] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 3258 AVX512VLBW :{EVEX} VPADDB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3259 AVX512VLBW :{EVEX} VPADDB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3260 AVX512BW :{EVEX} VPADDB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3261 AVX512VLBW :{EVEX} VPADDSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3262 AVX512VLBW :{EVEX} VPADDSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3263 AVX512BW :{EVEX} VPADDSB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3264 AVX512VLBW :{EVEX} VPADDUSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3265 AVX512VLBW :{EVEX} VPADDUSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3266 AVX512BW :{EVEX} VPADDUSB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3267 AVX512VLBW :{EVEX} VPADDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3268 AVX512VLBW :{EVEX} VPADDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3269 AVX512BW :{EVEX} VPADDW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3270 AVX512VLBW :{EVEX} VPADDSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3271 AVX512VLBW :{EVEX} VPADDSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3272 AVX512BW :{EVEX} VPADDSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3273 AVX512VLBW :{EVEX} VPADDUSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3274 AVX512VLBW :{EVEX} VPADDUSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3275 AVX512BW :{EVEX} VPADDUSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3276 AVX512VL :{EVEX} VPADDD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3277 AVX512VL :{EVEX} VPADDD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3278 AVX512F :{EVEX} VPADDD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3279 AVX512VL :{EVEX} VPADDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3280 AVX512VL :{EVEX} VPADDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3281 AVX512F :{EVEX} VPADDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3282 AVX512VLBW :{EVEX} VPSUBB xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3283 AVX512VLBW :{EVEX} VPSUBB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3284 AVX512VLBW :{EVEX} VPSUBB ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3285 AVX512VLBW :{EVEX} VPSUBB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3286 AVX512BW :{EVEX} VPSUBB zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3287 AVX512BW :{EVEX} VPSUBB zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3288 AVX512VLBW :{EVEX} VPSUBSB xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3289 AVX512VLBW :{EVEX} VPSUBSB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3290 AVX512VLBW :{EVEX} VPSUBSB ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3291 AVX512VLBW :{EVEX} VPSUBSB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3292 AVX512BW :{EVEX} VPSUBSB zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3293 AVX512BW :{EVEX} VPSUBSB zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3294 AVX512VLBW :{EVEX} VPSUBUSB xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3295 AVX512VLBW :{EVEX} VPSUBUSB xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3296 AVX512VLBW :{EVEX} VPSUBUSB ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3297 AVX512VLBW :{EVEX} VPSUBUSB ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3298 AVX512BW :{EVEX} VPSUBUSB zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3299 AVX512BW :{EVEX} VPSUBUSB zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3300 AVX512VLBW :{EVEX} VPSUBW xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3301 AVX512VLBW :{EVEX} VPSUBW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3302 AVX512VLBW :{EVEX} VPSUBW ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3303 AVX512VLBW :{EVEX} VPSUBW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3304 AVX512BW :{EVEX} VPSUBW zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3305 AVX512BW :{EVEX} VPSUBW zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3306 AVX512VLBW :{EVEX} VPSUBSW xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3307 AVX512VLBW :{EVEX} VPSUBSW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3308 AVX512VLBW :{EVEX} VPSUBSW ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3309 AVX512VLBW :{EVEX} VPSUBSW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3310 AVX512BW :{EVEX} VPSUBSW zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3311 AVX512BW :{EVEX} VPSUBSW zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3312 AVX512VLBW :{EVEX} VPSUBUSW xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3313 AVX512VLBW :{EVEX} VPSUBUSW xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3314 AVX512VLBW :{EVEX} VPSUBUSW ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3315 AVX512VLBW :{EVEX} VPSUBUSW ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3316 AVX512BW :{EVEX} VPSUBUSW zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3317 AVX512BW :{EVEX} VPSUBUSW zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3318 AVX512VL :{EVEX} VPSUBD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3319 AVX512VL :{EVEX} VPSUBD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3320 AVX512VL :{EVEX} VPSUBD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3321 AVX512VL :{EVEX} VPSUBD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3322 AVX512F :{EVEX} VPSUBD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3323 AVX512F :{EVEX} VPSUBD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3324 AVX512VL :{EVEX} VPSUBQ xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3325 AVX512VL :{EVEX} VPSUBQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3326 AVX512VL :{EVEX} VPSUBQ ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3327 AVX512VL :{EVEX} VPSUBQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3328 AVX512F :{EVEX} VPSUBQ zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3329 AVX512F :{EVEX} VPSUBQ zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3330 AVX512VLBW :{EVEX} VPMULLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3331 AVX512VLBW :{EVEX} VPMULLW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3332 AVX512BW :{EVEX} VPMULLW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3333 AVX512VLBW :{EVEX} VPMULHW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3334 AVX512VLBW :{EVEX} VPMULHW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3335 AVX512BW :{EVEX} VPMULHW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3336 AVX512VLBW :{EVEX} VPMULHUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3337 AVX512VLBW :{EVEX} VPMULHUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3338 AVX512BW :{EVEX} VPMULHUW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3339 AVX512VLBW :{EVEX} VPMULHRSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3340 AVX512VLBW :{EVEX} VPMULHRSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3341 AVX512BW :{EVEX} VPMULHRSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3342 AVX512VL :{EVEX} VPMULDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3343 AVX512VL :{EVEX} VPMULDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3344 AVX512F :{EVEX} VPMULDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3345 AVX512VL :{EVEX} VPMULUDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3346 AVX512VL :{EVEX} VPMULUDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3347 AVX512F :{EVEX} VPMULUDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3348 AVX512VL :{EVEX} VPMULLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3349 AVX512VL :{EVEX} VPMULLD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3350 AVX512F :{EVEX} VPMULLD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3351 AVX512VLDQ :{EVEX} VPMULLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3352 AVX512VLDQ :{EVEX} VPMULLQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3353 AVX512DQ :{EVEX} VPMULLQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3354 AVX512VLBW :{EVEX} VPMADDUBSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3355 AVX512VLBW :{EVEX} VPMADDUBSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3356 AVX512BW :{EVEX} VPMADDUBSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3357 AVX512VLBW :{EVEX} VPMADDWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3358 AVX512VLBW :{EVEX} VPMADDWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3359 AVX512BW :{EVEX} VPMADDWD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3360 AVX512VL_IFMA :{EVEX} VPMADD52LUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3361 AVX512VL_IFMA :{EVEX} VPMADD52LUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3362 AVX512_IFMA :{EVEX} VPMADD52LUQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3363 AVX512VL_IFMA :{EVEX} VPMADD52HUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3364 AVX512VL_IFMA :{EVEX} VPMADD52HUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3365 AVX512_IFMA :{EVEX} VPMADD52HUQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3366 AVX512VLBW :{EVEX} VPMINSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3367 AVX512VLBW :{EVEX} VPMINSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3368 AVX512BW :{EVEX} VPMINSB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3369 AVX512VLBW :{EVEX} VPMINUB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3370 AVX512VLBW :{EVEX} VPMINUB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3371 AVX512BW :{EVEX} VPMINUB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3372 AVX512VLBW :{EVEX} VPMINSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3373 AVX512VLBW :{EVEX} VPMINSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3374 AVX512BW :{EVEX} VPMINSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3375 AVX512VLBW :{EVEX} VPMINUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3376 AVX512VLBW :{EVEX} VPMINUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3377 AVX512BW :{EVEX} VPMINUW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3378 AVX512VL :{EVEX} VPMINSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3379 AVX512VL :{EVEX} VPMINSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3380 AVX512F :{EVEX} VPMINSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3381 AVX512VL :{EVEX} VPMINUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3382 AVX512VL :{EVEX} VPMINUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3383 AVX512F :{EVEX} VPMINUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3384 AVX512VL :{EVEX} VPMINSQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3385 AVX512VL :{EVEX} VPMINSQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3386 AVX512F :{EVEX} VPMINSQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3387 AVX512VL :{EVEX} VPMINUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3388 AVX512VL :{EVEX} VPMINUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3389 AVX512F :{EVEX} VPMINUQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3390 AVX512VLBW :{EVEX} VPMAXSB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3391 AVX512VLBW :{EVEX} VPMAXSB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3392 AVX512BW :{EVEX} VPMAXSB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3393 AVX512VLBW :{EVEX} VPMAXUB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3394 AVX512VLBW :{EVEX} VPMAXUB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3395 AVX512BW :{EVEX} VPMAXUB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3396 AVX512VLBW :{EVEX} VPMAXSW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3397 AVX512VLBW :{EVEX} VPMAXSW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3398 AVX512BW :{EVEX} VPMAXSW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3399 AVX512VLBW :{EVEX} VPMAXUW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3400 AVX512VLBW :{EVEX} VPMAXUW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3401 AVX512BW :{EVEX} VPMAXUW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3402 AVX512VL :{EVEX} VPMAXSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3403 AVX512VL :{EVEX} VPMAXSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3404 AVX512F :{EVEX} VPMAXSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3405 AVX512VL :{EVEX} VPMAXUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3406 AVX512VL :{EVEX} VPMAXUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3407 AVX512F :{EVEX} VPMAXUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3408 AVX512VL :{EVEX} VPMAXSQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3409 AVX512VL :{EVEX} VPMAXSQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3410 AVX512F :{EVEX} VPMAXSQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3411 AVX512VL :{EVEX} VPMAXUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3412 AVX512VL :{EVEX} VPMAXUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3413 AVX512F :{EVEX} VPMAXUQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3414 AVX512VLBW :{EVEX} VPCMPB k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3415 AVX512VLBW :{EVEX} VPCMPB k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3416 AVX512BW :{EVEX} VPCMPB k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3417 AVX512VLBW :{EVEX} VPCMPUB k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3418 AVX512VLBW :{EVEX} VPCMPUB k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3419 AVX512BW :{EVEX} VPCMPUB k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3420 AVX512VLBW :{EVEX} VPCMPW k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3421 AVX512VLBW :{EVEX} VPCMPW k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3422 AVX512BW :{EVEX} VPCMPW k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3423 AVX512VLBW :{EVEX} VPCMPUW k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3424 AVX512VLBW :{EVEX} VPCMPUW k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3425 AVX512BW :{EVEX} VPCMPUW k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3426 AVX512VL :{EVEX} VPCMPD k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3427 AVX512VL :{EVEX} VPCMPD k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3428 AVX512F :{EVEX} VPCMPD k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3429 AVX512VL :{EVEX} VPCMPUD k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3430 AVX512VL :{EVEX} VPCMPUD k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3431 AVX512F :{EVEX} VPCMPUD k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3432 AVX512VL :{EVEX} VPCMPQ k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3433 AVX512VL :{EVEX} VPCMPQ k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3434 AVX512F :{EVEX} VPCMPQ k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3435 AVX512VL :{EVEX} VPCMPUQ k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3436 AVX512VL :{EVEX} VPCMPUQ k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3437 AVX512F :{EVEX} VPCMPUQ k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 3438 AVX512VLBW :{EVEX} VPCMPEQB k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3439 AVX512VLBW :{EVEX} VPCMPEQB k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3440 AVX512BW :{EVEX} VPCMPEQB k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3441 AVX512VLBW :{EVEX} VPCMPEQW k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3442 AVX512VLBW :{EVEX} VPCMPEQW k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3443 AVX512BW :{EVEX} VPCMPEQW k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3444 AVX512VL :{EVEX} VPCMPEQD k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3445 AVX512VL :{EVEX} VPCMPEQD k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3446 AVX512F :{EVEX} VPCMPEQD k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3447 AVX512VL :{EVEX} VPCMPEQQ k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3448 AVX512VL :{EVEX} VPCMPEQQ k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3449 AVX512F :{EVEX} VPCMPEQQ k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3450 AVX512VLBW :{EVEX} VPCMPGTB k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3451 AVX512VLBW :{EVEX} VPCMPGTB k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3452 AVX512BW :{EVEX} VPCMPGTB k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3453 AVX512VLBW :{EVEX} VPCMPGTW k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3454 AVX512VLBW :{EVEX} VPCMPGTW k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3455 AVX512BW :{EVEX} VPCMPGTW k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3456 AVX512VL :{EVEX} VPCMPGTD k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3457 AVX512VL :{EVEX} VPCMPGTD k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3458 AVX512F :{EVEX} VPCMPGTD k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3459 AVX512VL :{EVEX} VPCMPGTQ k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3460 AVX512VL :{EVEX} VPCMPGTQ k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3461 AVX512F :{EVEX} VPCMPGTQ k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3462 AVX512VLBW :{EVEX} VPTESTMB k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3463 AVX512VLBW :{EVEX} VPTESTMB k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3464 AVX512BW :{EVEX} VPTESTMB k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3465 AVX512VLBW :{EVEX} VPTESTMW k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3466 AVX512VLBW :{EVEX} VPTESTMW k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3467 AVX512BW :{EVEX} VPTESTMW k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3468 AVX512VL :{EVEX} VPTESTMD k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3469 AVX512VL :{EVEX} VPTESTMD k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3470 AVX512F :{EVEX} VPTESTMD k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3471 AVX512VL :{EVEX} VPTESTMQ k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3472 AVX512VL :{EVEX} VPTESTMQ k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3473 AVX512F :{EVEX} VPTESTMQ k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3474 AVX512VLBW :{EVEX} VPTESTNMB k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3475 AVX512VLBW :{EVEX} VPTESTNMB k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3476 AVX512BW :{EVEX} VPTESTNMB k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3477 AVX512VLBW :{EVEX} VPTESTNMW k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3478 AVX512VLBW :{EVEX} VPTESTNMW k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3479 AVX512BW :{EVEX} VPTESTNMW k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3480 AVX512VL :{EVEX} VPTESTNMD k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3481 AVX512VL :{EVEX} VPTESTNMD k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3482 AVX512F :{EVEX} VPTESTNMD k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3483 AVX512VL :{EVEX} VPTESTNMQ k1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3484 AVX512VL :{EVEX} VPTESTNMQ k1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3485 AVX512F :{EVEX} VPTESTNMQ k1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3486 AVX512VL :{EVEX} VPANDD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3487 AVX512VL :{EVEX} VPANDD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3488 AVX512VL :{EVEX} VPANDD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3489 AVX512VL :{EVEX} VPANDD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3490 AVX512F :{EVEX} VPANDD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3491 AVX512F :{EVEX} VPANDD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3492 AVX512VL :{EVEX} VPANDQ xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3493 AVX512VL :{EVEX} VPANDQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3494 AVX512VL :{EVEX} VPANDQ ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3495 AVX512VL :{EVEX} VPANDQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3496 AVX512F :{EVEX} VPANDQ zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3497 AVX512F :{EVEX} VPANDQ zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3498 AVX512VL :{EVEX} VPANDND xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3499 AVX512VL :{EVEX} VPANDND xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3500 AVX512VL :{EVEX} VPANDND ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3501 AVX512VL :{EVEX} VPANDND ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3502 AVX512F :{EVEX} VPANDND zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3503 AVX512F :{EVEX} VPANDND zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3504 AVX512VL :{EVEX} VPANDNQ xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3505 AVX512VL :{EVEX} VPANDNQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3506 AVX512VL :{EVEX} VPANDNQ ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3507 AVX512VL :{EVEX} VPANDNQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3508 AVX512F :{EVEX} VPANDNQ zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3509 AVX512F :{EVEX} VPANDNQ zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3510 AVX512VL :{EVEX} VPORD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3511 AVX512VL :{EVEX} VPORD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3512 AVX512VL :{EVEX} VPORD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3513 AVX512VL :{EVEX} VPORD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3514 AVX512F :{EVEX} VPORD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3515 AVX512F :{EVEX} VPORD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3516 AVX512VL :{EVEX} VPORQ xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3517 AVX512VL :{EVEX} VPORQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3518 AVX512VL :{EVEX} VPORQ ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3519 AVX512VL :{EVEX} VPORQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3520 AVX512F :{EVEX} VPORQ zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3521 AVX512F :{EVEX} VPORQ zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3522 AVX512VL :{EVEX} VPXORD xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3523 AVX512VL :{EVEX} VPXORD xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3524 AVX512VL :{EVEX} VPXORD ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3525 AVX512VL :{EVEX} VPXORD ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3526 AVX512F :{EVEX} VPXORD zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3527 AVX512F :{EVEX} VPXORD zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3528 AVX512VL :{EVEX} VPXORQ xmm1, xmm1, xmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3529 AVX512VL :{EVEX} VPXORQ xmm1, xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3530 AVX512VL :{EVEX} VPXORQ ymm1, ymm1, ymm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3531 AVX512VL :{EVEX} VPXORQ ymm1, ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3532 AVX512F :{EVEX} VPXORQ zmm1, zmm1, zmm1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3533 AVX512F :{EVEX} VPXORQ zmm1, zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3534 AVX512VLBW :{EVEX} VPMOVWB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3535 AVX512VLBW :{EVEX} VPMOVWB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3536 AVX512BW :{EVEX} VPMOVWB ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3537 AVX512VL :{EVEX} VPMOVDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3538 AVX512VL :{EVEX} VPMOVDB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3539 AVX512F :{EVEX} VPMOVDB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3540 AVX512VL :{EVEX} VPMOVDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3541 AVX512VL :{EVEX} VPMOVDW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3542 AVX512F :{EVEX} VPMOVDW ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3543 AVX512VL :{EVEX} VPMOVQB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3544 AVX512VL :{EVEX} VPMOVQB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3545 AVX512F :{EVEX} VPMOVQB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3546 AVX512VL :{EVEX} VPMOVQW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3547 AVX512VL :{EVEX} VPMOVQW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3548 AVX512F :{EVEX} VPMOVQW xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3549 AVX512VL :{EVEX} VPMOVQD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3550 AVX512VL :{EVEX} VPMOVQD xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3551 AVX512F :{EVEX} VPMOVQD ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3552 AVX512VLBW :{EVEX} VPMOVSWB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3553 AVX512VLBW :{EVEX} VPMOVSWB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3554 AVX512BW :{EVEX} VPMOVSWB ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3555 AVX512VL :{EVEX} VPMOVSDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3556 AVX512VL :{EVEX} VPMOVSDB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3557 AVX512F :{EVEX} VPMOVSDB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3558 AVX512VL :{EVEX} VPMOVSDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3559 AVX512VL :{EVEX} VPMOVSDW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3560 AVX512F :{EVEX} VPMOVSDW ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3561 AVX512VL :{EVEX} VPMOVSQB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3562 AVX512VL :{EVEX} VPMOVSQB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3563 AVX512F :{EVEX} VPMOVSQB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3564 AVX512VL :{EVEX} VPMOVSQW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3565 AVX512VL :{EVEX} VPMOVSQW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3566 AVX512F :{EVEX} VPMOVSQW xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3567 AVX512VL :{EVEX} VPMOVSQD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3568 AVX512VL :{EVEX} VPMOVSQD xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3569 AVX512F :{EVEX} VPMOVSQD ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3570 AVX512VLBW :{EVEX} VPMOVUSWB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3571 AVX512VLBW :{EVEX} VPMOVUSWB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3572 AVX512BW :{EVEX} VPMOVUSWB ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3573 AVX512VL :{EVEX} VPMOVUSDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3574 AVX512VL :{EVEX} VPMOVUSDB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3575 AVX512F :{EVEX} VPMOVUSDB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3576 AVX512VL :{EVEX} VPMOVUSDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3577 AVX512VL :{EVEX} VPMOVUSDW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3578 AVX512F :{EVEX} VPMOVUSDW ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3579 AVX512VL :{EVEX} VPMOVUSQB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3580 AVX512VL :{EVEX} VPMOVUSQB xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3581 AVX512F :{EVEX} VPMOVUSQB xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3582 AVX512VL :{EVEX} VPMOVUSQW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3583 AVX512VL :{EVEX} VPMOVUSQW xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3584 AVX512F :{EVEX} VPMOVUSQW xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3585 AVX512VL :{EVEX} VPMOVUSQD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3586 AVX512VL :{EVEX} VPMOVUSQD xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3587 AVX512F :{EVEX} VPMOVUSQD ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3588 AVX512VLBW :{EVEX} VPMOVSXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3589 AVX512VLBW :{EVEX} VPMOVSXBW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3590 AVX512BW :{EVEX} VPMOVSXBW zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3591 AVX512VL :{EVEX} VPMOVSXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3592 AVX512VL :{EVEX} VPMOVSXBD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3593 AVX512F :{EVEX} VPMOVSXBD zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3594 AVX512VL :{EVEX} VPMOVSXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3595 AVX512VL :{EVEX} VPMOVSXBQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3596 AVX512F :{EVEX} VPMOVSXBQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3597 AVX512VL :{EVEX} VPMOVSXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3598 AVX512VL :{EVEX} VPMOVSXWD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3599 AVX512F :{EVEX} VPMOVSXWD zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3600 AVX512VL :{EVEX} VPMOVSXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3601 AVX512VL :{EVEX} VPMOVSXWQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3602 AVX512F :{EVEX} VPMOVSXWQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3603 AVX512VL :{EVEX} VPMOVSXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3604 AVX512VL :{EVEX} VPMOVSXDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3605 AVX512F :{EVEX} VPMOVSXDQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3606 AVX512VLBW :{EVEX} VPMOVZXBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3607 AVX512VLBW :{EVEX} VPMOVZXBW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3608 AVX512BW :{EVEX} VPMOVZXBW zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3609 AVX512VL :{EVEX} VPMOVZXBD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3610 AVX512VL :{EVEX} VPMOVZXBD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3611 AVX512F :{EVEX} VPMOVZXBD zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3612 AVX512VL :{EVEX} VPMOVZXBQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3613 AVX512VL :{EVEX} VPMOVZXBQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3614 AVX512F :{EVEX} VPMOVZXBQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3615 AVX512VL :{EVEX} VPMOVZXWD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3616 AVX512VL :{EVEX} VPMOVZXWD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3617 AVX512F :{EVEX} VPMOVZXWD zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3618 AVX512VL :{EVEX} VPMOVZXWQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3619 AVX512VL :{EVEX} VPMOVZXWQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3620 AVX512F :{EVEX} VPMOVZXWQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3621 AVX512VL :{EVEX} VPMOVZXDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3622 AVX512VL :{EVEX} VPMOVZXDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3623 AVX512F :{EVEX} VPMOVZXDQ zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3624 AVX512VLBW :{EVEX} VPABSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3625 AVX512VLBW :{EVEX} VPABSB ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3626 AVX512BW :{EVEX} VPABSB zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3627 AVX512VLBW :{EVEX} VPABSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3628 AVX512VLBW :{EVEX} VPABSW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3629 AVX512BW :{EVEX} VPABSW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3630 AVX512VL :{EVEX} VPABSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3631 AVX512VL :{EVEX} VPABSD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3632 AVX512F :{EVEX} VPABSD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3633 AVX512VL :{EVEX} VPABSQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3634 AVX512VL :{EVEX} VPABSQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3635 AVX512F :{EVEX} VPABSQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3636 AVX512VLBW :{EVEX} VPSADBW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3637 AVX512VLBW :{EVEX} VPSADBW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3638 AVX512BW :{EVEX} VPSADBW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3639 AVX512VLBW :{EVEX} VDBPSADBW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3640 AVX512VLBW :{EVEX} VDBPSADBW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3641 AVX512BW :{EVEX} VDBPSADBW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3642 AVX512VLBW :{EVEX} VPALIGNR xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3643 AVX512VLBW :{EVEX} VPALIGNR ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3644 AVX512BW :{EVEX} VPALIGNR zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3645 AVX512VL :{EVEX} VALIGND xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3646 AVX512VL :{EVEX} VALIGND ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3647 AVX512F :{EVEX} VALIGND zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3648 AVX512VL :{EVEX} VALIGNQ xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3649 AVX512VL :{EVEX} VALIGNQ ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3650 AVX512F :{EVEX} VALIGNQ zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3651 AVX512VLBW :{EVEX} VPAVGB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3652 AVX512VLBW :{EVEX} VPAVGB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3653 AVX512BW :{EVEX} VPAVGB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3654 AVX512VLBW :{EVEX} VPAVGW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3655 AVX512VLBW :{EVEX} VPAVGW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3656 AVX512BW :{EVEX} VPAVGW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3657 AVX512VLBW :{EVEX} VPBLENDMB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3658 AVX512VLBW :{EVEX} VPBLENDMB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3659 AVX512BW :{EVEX} VPBLENDMB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3660 AVX512VLBW :{EVEX} VPBLENDMW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3661 AVX512VLBW :{EVEX} VPBLENDMW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3662 AVX512BW :{EVEX} VPBLENDMW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3663 AVX512VL :{EVEX} VPBLENDMD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3664 AVX512VL :{EVEX} VPBLENDMD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3665 AVX512F :{EVEX} VPBLENDMD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3666 AVX512VL :{EVEX} VPBLENDMQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3667 AVX512VL :{EVEX} VPBLENDMQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3668 AVX512F :{EVEX} VPBLENDMQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3669 AVX512VLCD :{EVEX} VPCONFLICTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3670 AVX512VLCD :{EVEX} VPCONFLICTD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3671 AVX512CD :{EVEX} VPCONFLICTD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3672 AVX512VLCD :{EVEX} VPCONFLICTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3673 AVX512VLCD :{EVEX} VPCONFLICTQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3674 AVX512CD :{EVEX} VPCONFLICTQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3675 AVX512VL :{EVEX} VPCOMPRESSD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3676 AVX512VL :{EVEX} VPCOMPRESSD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3677 AVX512F :{EVEX} VPCOMPRESSD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3678 AVX512VL :{EVEX} VPCOMPRESSQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3679 AVX512VL :{EVEX} VPCOMPRESSQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3680 AVX512F :{EVEX} VPCOMPRESSQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3681 AVX512VL :{EVEX} VPCOMPRESSD xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3682 AVX512VL :{EVEX} VPCOMPRESSD ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3683 AVX512F :{EVEX} VPCOMPRESSD zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3684 AVX512VL :{EVEX} VPCOMPRESSQ xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3685 AVX512VL :{EVEX} VPCOMPRESSQ ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3686 AVX512F :{EVEX} VPCOMPRESSQ zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3687 AVX512VL :{EVEX} VPEXPANDD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3688 AVX512VL :{EVEX} VPEXPANDD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3689 AVX512F :{EVEX} VPEXPANDD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3690 AVX512VL :{EVEX} VPEXPANDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3691 AVX512VL :{EVEX} VPEXPANDQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3692 AVX512F :{EVEX} VPEXPANDQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3693 AVX512VL :{EVEX} VPEXPANDD xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3694 AVX512VL :{EVEX} VPEXPANDD ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3695 AVX512F :{EVEX} VPEXPANDD zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3696 AVX512VL :{EVEX} VPEXPANDQ xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3697 AVX512VL :{EVEX} VPEXPANDQ ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3698 AVX512F :{EVEX} VPEXPANDQ zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3699 AVX512VLCD :{EVEX} VPLZCNTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3700 AVX512VLCD :{EVEX} VPLZCNTD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3701 AVX512CD :{EVEX} VPLZCNTD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3702 AVX512VLCD :{EVEX} VPLZCNTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3703 AVX512VLCD :{EVEX} VPLZCNTQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3704 AVX512CD :{EVEX} VPLZCNTQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3705 AVX512VL_VBMI :{EVEX} VPMULTISHIFTQB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3706 AVX512VL_VBMI :{EVEX} VPMULTISHIFTQB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3707 AVX512_VBMI :{EVEX} VPMULTISHIFTQB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3708 AVX512VLBW :{EVEX} VPSLLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3709 AVX512VLBW :{EVEX} VPSLLW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3710 AVX512BW :{EVEX} VPSLLW zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3711 AVX512VL :{EVEX} VPSLLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3712 AVX512VL :{EVEX} VPSLLD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3713 AVX512F :{EVEX} VPSLLD zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3714 AVX512VL :{EVEX} VPSLLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3715 AVX512VL :{EVEX} VPSLLQ ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3716 AVX512F :{EVEX} VPSLLQ zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3717 AVX512VLBW :{EVEX} VPSLLW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3718 AVX512VLBW :{EVEX} VPSLLW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3719 AVX512BW :{EVEX} VPSLLW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3720 AVX512VL :{EVEX} VPSLLD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3721 AVX512VL :{EVEX} VPSLLD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3722 AVX512F :{EVEX} VPSLLD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3723 AVX512VL :{EVEX} VPSLLQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3724 AVX512VL :{EVEX} VPSLLQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3725 AVX512F :{EVEX} VPSLLQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3726 AVX512VLBW :{EVEX} VPSLLDQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3727 AVX512VLBW :{EVEX} VPSLLDQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3728 AVX512BW :{EVEX} VPSLLDQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3729 AVX512VLBW :{EVEX} VPSLLVW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3730 AVX512VLBW :{EVEX} VPSLLVW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3731 AVX512BW :{EVEX} VPSLLVW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3732 AVX512VL :{EVEX} VPSLLVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3733 AVX512VL :{EVEX} VPSLLVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3734 AVX512F :{EVEX} VPSLLVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3735 AVX512VL :{EVEX} VPSLLVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3736 AVX512VL :{EVEX} VPSLLVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3737 AVX512F :{EVEX} VPSLLVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3738 AVX512VLBW :{EVEX} VPSRLW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3739 AVX512VLBW :{EVEX} VPSRLW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3740 AVX512BW :{EVEX} VPSRLW zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3741 AVX512VL :{EVEX} VPSRLD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3742 AVX512VL :{EVEX} VPSRLD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3743 AVX512F :{EVEX} VPSRLD zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3744 AVX512VL :{EVEX} VPSRLQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3745 AVX512VL :{EVEX} VPSRLQ ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3746 AVX512F :{EVEX} VPSRLQ zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3747 AVX512VLBW :{EVEX} VPSRLW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3748 AVX512VLBW :{EVEX} VPSRLW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3749 AVX512BW :{EVEX} VPSRLW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3750 AVX512VL :{EVEX} VPSRLD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3751 AVX512VL :{EVEX} VPSRLD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3752 AVX512F :{EVEX} VPSRLD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3753 AVX512VL :{EVEX} VPSRLQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3754 AVX512VL :{EVEX} VPSRLQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3755 AVX512F :{EVEX} VPSRLQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3756 AVX512VLBW :{EVEX} VPSRLDQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3757 AVX512VLBW :{EVEX} VPSRLDQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3758 AVX512BW :{EVEX} VPSRLDQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3759 AVX512VLBW :{EVEX} VPSRLVW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3760 AVX512VLBW :{EVEX} VPSRLVW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3761 AVX512BW :{EVEX} VPSRLVW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3762 AVX512VL :{EVEX} VPSRLVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3763 AVX512VL :{EVEX} VPSRLVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3764 AVX512F :{EVEX} VPSRLVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3765 AVX512VL :{EVEX} VPSRLVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3766 AVX512VL :{EVEX} VPSRLVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3767 AVX512F :{EVEX} VPSRLVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3768 AVX512VLBW :{EVEX} VPSRAW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3769 AVX512VLBW :{EVEX} VPSRAW ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3770 AVX512BW :{EVEX} VPSRAW zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3771 AVX512VL :{EVEX} VPSRAD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3772 AVX512VL :{EVEX} VPSRAD ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3773 AVX512F :{EVEX} VPSRAD zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3774 AVX512VL :{EVEX} VPSRAQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3775 AVX512VL :{EVEX} VPSRAQ ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3776 AVX512F :{EVEX} VPSRAQ zmm, zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3777 AVX512VLBW :{EVEX} VPSRAW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3778 AVX512VLBW :{EVEX} VPSRAW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3779 AVX512BW :{EVEX} VPSRAW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3780 AVX512VL :{EVEX} VPSRAD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3781 AVX512VL :{EVEX} VPSRAD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3782 AVX512F :{EVEX} VPSRAD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3783 AVX512VL :{EVEX} VPSRAQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3784 AVX512VL :{EVEX} VPSRAQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3785 AVX512F :{EVEX} VPSRAQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3786 AVX512VLBW :{EVEX} VPSRAVW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3787 AVX512VLBW :{EVEX} VPSRAVW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3788 AVX512BW :{EVEX} VPSRAVW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3789 AVX512VL :{EVEX} VPSRAVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3790 AVX512VL :{EVEX} VPSRAVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3791 AVX512F :{EVEX} VPSRAVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3792 AVX512VL :{EVEX} VPSRAVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3793 AVX512VL :{EVEX} VPSRAVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3794 AVX512F :{EVEX} VPSRAVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3795 AVX512VL :{EVEX} VPROLD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3796 AVX512VL :{EVEX} VPROLD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3797 AVX512F :{EVEX} VPROLD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3798 AVX512VL :{EVEX} VPROLQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3799 AVX512VL :{EVEX} VPROLQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3800 AVX512F :{EVEX} VPROLQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3801 AVX512VL :{EVEX} VPROLVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3802 AVX512VL :{EVEX} VPROLVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3803 AVX512F :{EVEX} VPROLVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3804 AVX512VL :{EVEX} VPROLVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3805 AVX512VL :{EVEX} VPROLVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3806 AVX512F :{EVEX} VPROLVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3807 AVX512VL :{EVEX} VPRORD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3808 AVX512VL :{EVEX} VPRORD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3809 AVX512F :{EVEX} VPRORD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3810 AVX512VL :{EVEX} VPRORQ xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3811 AVX512VL :{EVEX} VPRORQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3812 AVX512F :{EVEX} VPRORQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3813 AVX512VL :{EVEX} VPRORVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3814 AVX512VL :{EVEX} VPRORVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3815 AVX512F :{EVEX} VPRORVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3816 AVX512VL :{EVEX} VPRORVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3817 AVX512VL :{EVEX} VPRORVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3818 AVX512F :{EVEX} VPRORVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3819 AVX512VL :{EVEX} VPTERNLOGD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3820 AVX512VL :{EVEX} VPTERNLOGD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3821 AVX512F :{EVEX} VPTERNLOGD zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3822 AVX512VL :{EVEX} VPTERNLOGQ xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3823 AVX512VL :{EVEX} VPTERNLOGQ ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3824 AVX512F :{EVEX} VPTERNLOGQ zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3825 AVX512F :{EVEX} VMOVD r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3826 AVX512F :{EVEX} VMOVD xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 3827 AVX512F :{EVEX} VMOVD r32, xmm + xmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3828 AVX512F :{EVEX} VMOVD xmm, [m32] L: [memory dep.] T: 0.00ns= 0.000c 3829 AVX512F :{EVEX} VMOVD [m32], xmm L: [memory dep.] T: 0.00ns= 0.000c 3830 AVX512F :{EVEX} VMOVD xmm, [m32] + [m32], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3831 AVX512F_X64 :{EVEX} VMOVQ r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3832 AVX512F_X64 :{EVEX} VMOVQ xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 3833 AVX512F_X64 :{EVEX} VMOVQ r64, xmm + xmm, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3834 AVX512F_X64 :{EVEX} VMOVQ xmm, [m64] L: [memory dep.] T: 0.00ns= 0.000c 3835 AVX512F_X64 :{EVEX} VMOVQ [m64], xmm L: [memory dep.] T: 0.00ns= 0.000c 3836 AVX512F_X64 :{EVEX} VMOVQ xmm, [m64] + [m64], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3837 AVX512VL :{EVEX} VMOVDQA32 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3838 AVX512VL :{EVEX} VMOVDQA32 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3839 AVX512VL :{EVEX} VMOVDQA32 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3840 AVX512VL :{EVEX} VMOVDQA32 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3841 AVX512F :{EVEX} VMOVDQA32 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3842 AVX512F :{EVEX} VMOVDQA32 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3843 AVX512VL :{EVEX} VMOVDQA32 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3844 AVX512VL :{EVEX} VMOVDQA32 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3845 AVX512F :{EVEX} VMOVDQA32 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3846 AVX512VL :{EVEX} VMOVDQA32 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3847 AVX512VL :{EVEX} VMOVDQA32 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3848 AVX512F :{EVEX} VMOVDQA32 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3849 AVX512VL :{EVEX} VMOVDQA32 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3850 AVX512VL :{EVEX} VMOVDQA32 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3851 AVX512F :{EVEX} VMOVDQA32 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3852 AVX512VL :{EVEX} VMOVDQA64 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3853 AVX512VL :{EVEX} VMOVDQA64 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3854 AVX512VL :{EVEX} VMOVDQA64 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3855 AVX512VL :{EVEX} VMOVDQA64 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3856 AVX512F :{EVEX} VMOVDQA64 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3857 AVX512F :{EVEX} VMOVDQA64 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3858 AVX512VL :{EVEX} VMOVDQA64 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3859 AVX512VL :{EVEX} VMOVDQA64 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3860 AVX512F :{EVEX} VMOVDQA64 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3861 AVX512VL :{EVEX} VMOVDQA64 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3862 AVX512VL :{EVEX} VMOVDQA64 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3863 AVX512F :{EVEX} VMOVDQA64 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3864 AVX512VL :{EVEX} VMOVDQA64 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3865 AVX512VL :{EVEX} VMOVDQA64 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3866 AVX512F :{EVEX} VMOVDQA64 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3867 AVX512VLBW :{EVEX} VMOVDQU8 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3868 AVX512VLBW :{EVEX} VMOVDQU8 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3869 AVX512VLBW :{EVEX} VMOVDQU8 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3870 AVX512VLBW :{EVEX} VMOVDQU8 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3871 AVX512BW :{EVEX} VMOVDQU8 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3872 AVX512BW :{EVEX} VMOVDQU8 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3873 AVX512VLBW :{EVEX} VMOVDQU8 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3874 AVX512VLBW :{EVEX} VMOVDQU8 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3875 AVX512BW :{EVEX} VMOVDQU8 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3876 AVX512VLBW :{EVEX} VMOVDQU8 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3877 AVX512VLBW :{EVEX} VMOVDQU8 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3878 AVX512BW :{EVEX} VMOVDQU8 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3879 AVX512VLBW :{EVEX} VMOVDQU8 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3880 AVX512VLBW :{EVEX} VMOVDQU8 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3881 AVX512BW :{EVEX} VMOVDQU8 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3882 AVX512VLBW :{EVEX} VMOVDQU8 xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3883 AVX512VLBW :{EVEX} VMOVDQU8 ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3884 AVX512BW :{EVEX} VMOVDQU8 zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3885 AVX512VLBW :{EVEX} VMOVDQU8 [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3886 AVX512VLBW :{EVEX} VMOVDQU8 [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3887 AVX512BW :{EVEX} VMOVDQU8 [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3888 AVX512VLBW :{EVEX} VMOVDQU8 xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3889 AVX512VLBW :{EVEX} VMOVDQU8 ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3890 AVX512BW :{EVEX} VMOVDQU8 zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3891 AVX512VLBW :{EVEX} VMOVDQU16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3892 AVX512VLBW :{EVEX} VMOVDQU16 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3893 AVX512VLBW :{EVEX} VMOVDQU16 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3894 AVX512VLBW :{EVEX} VMOVDQU16 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3895 AVX512BW :{EVEX} VMOVDQU16 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3896 AVX512BW :{EVEX} VMOVDQU16 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3897 AVX512VLBW :{EVEX} VMOVDQU16 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3898 AVX512VLBW :{EVEX} VMOVDQU16 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3899 AVX512BW :{EVEX} VMOVDQU16 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3900 AVX512VLBW :{EVEX} VMOVDQU16 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3901 AVX512VLBW :{EVEX} VMOVDQU16 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3902 AVX512BW :{EVEX} VMOVDQU16 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3903 AVX512VLBW :{EVEX} VMOVDQU16 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3904 AVX512VLBW :{EVEX} VMOVDQU16 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3905 AVX512BW :{EVEX} VMOVDQU16 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3906 AVX512VLBW :{EVEX} VMOVDQU16 xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3907 AVX512VLBW :{EVEX} VMOVDQU16 ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3908 AVX512BW :{EVEX} VMOVDQU16 zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3909 AVX512VLBW :{EVEX} VMOVDQU16 [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3910 AVX512VLBW :{EVEX} VMOVDQU16 [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3911 AVX512BW :{EVEX} VMOVDQU16 [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3912 AVX512VLBW :{EVEX} VMOVDQU16 xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3913 AVX512VLBW :{EVEX} VMOVDQU16 ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3914 AVX512BW :{EVEX} VMOVDQU16 zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3915 AVX512VL :{EVEX} VMOVDQU32 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3916 AVX512VL :{EVEX} VMOVDQU32 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3917 AVX512VL :{EVEX} VMOVDQU32 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3918 AVX512VL :{EVEX} VMOVDQU32 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3919 AVX512F :{EVEX} VMOVDQU32 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3920 AVX512F :{EVEX} VMOVDQU32 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3921 AVX512VL :{EVEX} VMOVDQU32 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3922 AVX512VL :{EVEX} VMOVDQU32 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3923 AVX512F :{EVEX} VMOVDQU32 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3924 AVX512VL :{EVEX} VMOVDQU32 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3925 AVX512VL :{EVEX} VMOVDQU32 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3926 AVX512F :{EVEX} VMOVDQU32 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3927 AVX512VL :{EVEX} VMOVDQU32 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3928 AVX512VL :{EVEX} VMOVDQU32 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3929 AVX512F :{EVEX} VMOVDQU32 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3930 AVX512VL :{EVEX} VMOVDQU32 xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3931 AVX512VL :{EVEX} VMOVDQU32 ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3932 AVX512F :{EVEX} VMOVDQU32 zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3933 AVX512VL :{EVEX} VMOVDQU32 [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3934 AVX512VL :{EVEX} VMOVDQU32 [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3935 AVX512F :{EVEX} VMOVDQU32 [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3936 AVX512VL :{EVEX} VMOVDQU32 xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3937 AVX512VL :{EVEX} VMOVDQU32 ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3938 AVX512F :{EVEX} VMOVDQU32 zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3939 AVX512VL :{EVEX} VMOVDQU64 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3940 AVX512VL :{EVEX} VMOVDQU64 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3941 AVX512VL :{EVEX} VMOVDQU64 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3942 AVX512VL :{EVEX} VMOVDQU64 ymm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3943 AVX512F :{EVEX} VMOVDQU64 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3944 AVX512F :{EVEX} VMOVDQU64 zmm1, zmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3945 AVX512VL :{EVEX} VMOVDQU64 xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3946 AVX512VL :{EVEX} VMOVDQU64 ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3947 AVX512F :{EVEX} VMOVDQU64 zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3948 AVX512VL :{EVEX} VMOVDQU64 [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3949 AVX512VL :{EVEX} VMOVDQU64 [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3950 AVX512F :{EVEX} VMOVDQU64 [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3951 AVX512VL :{EVEX} VMOVDQU64 xmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3952 AVX512VL :{EVEX} VMOVDQU64 ymm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3953 AVX512F :{EVEX} VMOVDQU64 zmm LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3954 AVX512VL :{EVEX} VMOVDQU64 xmm, [m128 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3955 AVX512VL :{EVEX} VMOVDQU64 ymm, [m256 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3956 AVX512F :{EVEX} VMOVDQU64 zmm, [m512 + 4] L: [memory dep.] T: 0.00ns= 0.000c 3957 AVX512VL :{EVEX} VMOVDQU64 [m128 + 4], xmm L: [memory dep.] T: 0.00ns= 0.000c 3958 AVX512VL :{EVEX} VMOVDQU64 [m256 + 4], ymm L: [memory dep.] T: 0.00ns= 0.000c 3959 AVX512F :{EVEX} VMOVDQU64 [m512 + 4], zmm L: [memory dep.] T: 0.00ns= 0.000c 3960 AVX512VL :{EVEX} VMOVDQU64 xmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3961 AVX512VL :{EVEX} VMOVDQU64 ymm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3962 AVX512F :{EVEX} VMOVDQU64 zmm + 4 LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3963 AVX512VL :{EVEX} VMOVNTDQA xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 3964 AVX512VL :{EVEX} VMOVNTDQA ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 3965 AVX512F :{EVEX} VMOVNTDQA zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 3966 AVX512VL :{EVEX} VMOVNTDQ [m128], xmm L: [memory dep.] T: 0.00ns= 0.000c 3967 AVX512VL :{EVEX} VMOVNTDQ [m256], ymm L: [memory dep.] T: 0.00ns= 0.000c 3968 AVX512F :{EVEX} VMOVNTDQ [m512], zmm L: [memory dep.] T: 0.00ns= 0.000c 3969 AVX512VL :{EVEX} VMOVNTDQA + VMOVNTDQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3970 AVX512VL :{EVEX} VMOVNTDQA + VMOVNTDQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3971 AVX512F :{EVEX} VMOVNTDQA + VMOVNTDQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3972 AVX512VLBW :{EVEX} VPMOVB2M k, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3973 AVX512VLBW :{EVEX} VPMOVB2M k, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3974 AVX512BW :{EVEX} VPMOVB2M k, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3975 AVX512VLBW :{EVEX} VPMOVW2M k, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3976 AVX512VLBW :{EVEX} VPMOVW2M k, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3977 AVX512BW :{EVEX} VPMOVW2M k, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3978 AVX512VLDQ :{EVEX} VPMOVD2M k, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3979 AVX512VLDQ :{EVEX} VPMOVD2M k, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3980 AVX512DQ :{EVEX} VPMOVD2M k, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3981 AVX512VLDQ :{EVEX} VPMOVQ2M k, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 3982 AVX512VLDQ :{EVEX} VPMOVQ2M k, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 3983 AVX512DQ :{EVEX} VPMOVQ2M k, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 3984 AVX512VLBW :{EVEX} VPMOVM2B xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3985 AVX512VLBW :{EVEX} VPMOVM2B ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3986 AVX512BW :{EVEX} VPMOVM2B zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3987 AVX512VLBW :{EVEX} VPMOVM2W xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3988 AVX512VLBW :{EVEX} VPMOVM2W ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3989 AVX512BW :{EVEX} VPMOVM2W zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3990 AVX512VLDQ :{EVEX} VPMOVM2D xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3991 AVX512VLDQ :{EVEX} VPMOVM2D ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3992 AVX512DQ :{EVEX} VPMOVM2D zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3993 AVX512VLDQ :{EVEX} VPMOVM2Q xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3994 AVX512VLDQ :{EVEX} VPMOVM2Q ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3995 AVX512DQ :{EVEX} VPMOVM2Q zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 3996 AVX512VLBW :{EVEX} VPMOVB2M + VPMOVM2B xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3997 AVX512VLBW :{EVEX} VPMOVB2M + VPMOVM2B ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3998 AVX512BW :{EVEX} VPMOVB2M + VPMOVM2B zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 3999 AVX512VLBW :{EVEX} VPMOVW2M + VPMOVM2W xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4000 AVX512VLBW :{EVEX} VPMOVW2M + VPMOVM2W ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4001 AVX512BW :{EVEX} VPMOVW2M + VPMOVM2W zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4002 AVX512VLDQ :{EVEX} VPMOVD2M + VPMOVM2D xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4003 AVX512VLDQ :{EVEX} VPMOVD2M + VPMOVM2D ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4004 AVX512DQ :{EVEX} VPMOVD2M + VPMOVM2D zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4005 AVX512VLDQ :{EVEX} VPMOVQ2M + VPMOVM2Q xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4006 AVX512VLDQ :{EVEX} VPMOVQ2M + VPMOVM2Q ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4007 AVX512DQ :{EVEX} VPMOVQ2M + VPMOVM2Q zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4008 AVX512VLBW :{EVEX} VPBROADCASTB xmm, r8 L: [diff. reg. set] T: 0.00ns= 0.000c 4009 AVX512VLBW :{EVEX} VPBROADCASTB ymm, r8 L: [diff. reg. set] T: 0.00ns= 0.000c 4010 AVX512BW :{EVEX} VPBROADCASTB zmm, r8 L: [diff. reg. set] T: 0.00ns= 0.000c 4011 AVX512VLBW :{EVEX} VPBROADCASTW xmm, r16 L: [diff. reg. set] T: 0.00ns= 0.000c 4012 AVX512VLBW :{EVEX} VPBROADCASTW ymm, r16 L: [diff. reg. set] T: 0.00ns= 0.000c 4013 AVX512BW :{EVEX} VPBROADCASTW zmm, r16 L: [diff. reg. set] T: 0.00ns= 0.000c 4014 AVX512VL :{EVEX} VPBROADCASTD xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 4015 AVX512VL :{EVEX} VPBROADCASTD ymm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 4016 AVX512F :{EVEX} VPBROADCASTD zmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 4017 AVX512VL_X64 :{EVEX} VPBROADCASTQ xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 4018 AVX512VL_X64 :{EVEX} VPBROADCASTQ ymm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 4019 AVX512F_X64 :{EVEX} VPBROADCASTQ zmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 4020 AVX512VLBW :{EVEX} VPBROADCASTB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4021 AVX512VLBW :{EVEX} VPBROADCASTB ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4022 AVX512BW :{EVEX} VPBROADCASTB zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4023 AVX512VLBW :{EVEX} VPBROADCASTW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4024 AVX512VLBW :{EVEX} VPBROADCASTW ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4025 AVX512BW :{EVEX} VPBROADCASTW zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4026 AVX512VL :{EVEX} VPBROADCASTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4027 AVX512VL :{EVEX} VPBROADCASTD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4028 AVX512F :{EVEX} VPBROADCASTD zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4029 AVX512VL :{EVEX} VPBROADCASTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4030 AVX512VL :{EVEX} VPBROADCASTQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4031 AVX512F :{EVEX} VPBROADCASTQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4032 AVX512VLDQ :{EVEX} VBROADCASTI32X2 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4033 AVX512VLDQ :{EVEX} VBROADCASTI32X2 ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4034 AVX512DQ :{EVEX} VBROADCASTI32X2 zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4035 AVX512VL :{EVEX} VBROADCASTI32X4 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4036 AVX512F :{EVEX} VBROADCASTI32X4 zmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4037 AVX512DQ :{EVEX} VBROADCASTI32X8 zmm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4038 AVX512VLDQ :{EVEX} VBROADCASTI64X2 ymm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4039 AVX512DQ :{EVEX} VBROADCASTI64X2 zmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4040 AVX512F :{EVEX} VBROADCASTI64X4 zmm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4041 AVX512VLCD :{EVEX} VPBROADCASTMB2Q xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4042 AVX512VLCD :{EVEX} VPBROADCASTMB2Q ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4043 AVX512CD :{EVEX} VPBROADCASTMB2Q zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4044 AVX512VLCD :{EVEX} VPBROADCASTMW2D xmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4045 AVX512VLCD :{EVEX} VPBROADCASTMW2D ymm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4046 AVX512CD :{EVEX} VPBROADCASTMW2D zmm, k L: [diff. reg. set] T: 0.00ns= 0.000c 4047 AVX512BW :{EVEX} VPEXTRB r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4048 AVX512BW :{EVEX} VPEXTRW r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4049 AVX512DQ :{EVEX} VPEXTRD r32, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4050 AVX512DQ_X64 :{EVEX} VPEXTRQ r64, xmm, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4051 AVX512BW :{EVEX} VPINSRB xmm, xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4052 AVX512BW :{EVEX} VPINSRW xmm, xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4053 AVX512DQ :{EVEX} VPINSRD xmm, xmm, r32, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4054 AVX512DQ_X64 :{EVEX} VPINSRQ xmm, xmm, r64, im8 L: [diff. reg. set] T: 0.00ns= 0.000c 4055 AVX512BW :{EVEX} VPEXTRB + VPINSRB xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4056 AVX512BW :{EVEX} VPEXTRW + VPINSRW xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4057 AVX512DQ :{EVEX} VPEXTRD + VPINSRD xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4058 AVX512DQ_X64 :{EVEX} VPEXTRQ + VPINSRQ xmm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4059 AVX512VL :{EVEX} VEXTRACTI32X4 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4060 AVX512F :{EVEX} VEXTRACTI32X4 xmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4061 AVX512VL :{EVEX} VEXTRACTI32X4 [m128], ymm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4062 AVX512F :{EVEX} VEXTRACTI32X4 [m128], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4063 AVX512DQ :{EVEX} VEXTRACTI32X8 ymm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4064 AVX512DQ :{EVEX} VEXTRACTI32X8 [m256], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4065 AVX512VLDQ :{EVEX} VEXTRACTI64X2 xmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4066 AVX512DQ :{EVEX} VEXTRACTI64X2 xmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4067 AVX512VLDQ :{EVEX} VEXTRACTI64X2 [m128], ymm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4068 AVX512DQ :{EVEX} VEXTRACTI64X2 [m128], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4069 AVX512F :{EVEX} VEXTRACTI64X4 ymm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4070 AVX512F :{EVEX} VEXTRACTI64X4 [m256], zmm, imm8 L: [memory dep.] T: 0.00ns= 0.000c 4071 AVX512VL :{EVEX} VINSERTI32X4 ymm, ymm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4072 AVX512F :{EVEX} VINSERTI32X4 zmm, zmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4073 AVX512VL :{EVEX} VINSERTI32X4 ymm, ymm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4074 AVX512F :{EVEX} VINSERTI32X4 zmm, zmm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4075 AVX512DQ :{EVEX} VINSERTI32X8 zmm, zmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4076 AVX512DQ :{EVEX} VINSERTI32X8 zmm, zmm, [m256], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4077 AVX512VLDQ :{EVEX} VINSERTI64X2 ymm, ymm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4078 AVX512DQ :{EVEX} VINSERTI64X2 zmm, zmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4079 AVX512VLDQ :{EVEX} VINSERTI64X2 ymm, ymm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4080 AVX512DQ :{EVEX} VINSERTI64X2 zmm, zmm, [m128], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4081 AVX512F :{EVEX} VINSERTI64X4 zmm, zmm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4082 AVX512F :{EVEX} VINSERTI64X4 zmm, zmm, [m256], imm8 L: [memory dep.] T: 0.00ns= 0.000c 4083 AVX512VLBW :{EVEX} VPACKSSWB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4084 AVX512VLBW :{EVEX} VPACKSSWB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4085 AVX512BW :{EVEX} VPACKSSWB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4086 AVX512VLBW :{EVEX} VPACKUSWB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4087 AVX512VLBW :{EVEX} VPACKUSWB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4088 AVX512BW :{EVEX} VPACKUSWB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4089 AVX512VLBW :{EVEX} VPACKSSDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4090 AVX512VLBW :{EVEX} VPACKSSDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4091 AVX512BW :{EVEX} VPACKSSDW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4092 AVX512VLBW :{EVEX} VPACKUSDW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4093 AVX512VLBW :{EVEX} VPACKUSDW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4094 AVX512BW :{EVEX} VPACKUSDW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4095 AVX512VLBW :{EVEX} VPUNPCKLBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4096 AVX512VLBW :{EVEX} VPUNPCKLBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4097 AVX512BW :{EVEX} VPUNPCKLBW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4098 AVX512VLBW :{EVEX} VPUNPCKHBW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4099 AVX512VLBW :{EVEX} VPUNPCKHBW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4100 AVX512BW :{EVEX} VPUNPCKHBW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4101 AVX512VLBW :{EVEX} VPUNPCKLWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4102 AVX512VLBW :{EVEX} VPUNPCKLWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4103 AVX512BW :{EVEX} VPUNPCKLWD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4104 AVX512VLBW :{EVEX} VPUNPCKHWD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4105 AVX512VLBW :{EVEX} VPUNPCKHWD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4106 AVX512BW :{EVEX} VPUNPCKHWD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4107 AVX512VL :{EVEX} VPUNPCKLDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4108 AVX512VL :{EVEX} VPUNPCKLDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4109 AVX512F :{EVEX} VPUNPCKLDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4110 AVX512VL :{EVEX} VPUNPCKHDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4111 AVX512VL :{EVEX} VPUNPCKHDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4112 AVX512F :{EVEX} VPUNPCKHDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4113 AVX512VL :{EVEX} VPUNPCKLQDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4114 AVX512VL :{EVEX} VPUNPCKLQDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4115 AVX512F :{EVEX} VPUNPCKLQDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4116 AVX512VL :{EVEX} VPUNPCKHQDQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4117 AVX512VL :{EVEX} VPUNPCKHQDQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4118 AVX512F :{EVEX} VPUNPCKHQDQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4119 AVX512VLBW :{EVEX} VPSHUFB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4120 AVX512VLBW :{EVEX} VPSHUFB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4121 AVX512BW :{EVEX} VPSHUFB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4122 AVX512VLBW :{EVEX} VPSHUFLW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4123 AVX512VLBW :{EVEX} VPSHUFLW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4124 AVX512BW :{EVEX} VPSHUFLW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4125 AVX512VLBW :{EVEX} VPSHUFHW xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4126 AVX512VLBW :{EVEX} VPSHUFHW ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4127 AVX512BW :{EVEX} VPSHUFHW zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4128 AVX512VL :{EVEX} VPSHUFD xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4129 AVX512VL :{EVEX} VPSHUFD ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4130 AVX512F :{EVEX} VPSHUFD zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4131 AVX512VL :{EVEX} VSHUFI32X4 ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4132 AVX512F :{EVEX} VSHUFI32X4 zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4133 AVX512VL :{EVEX} VSHUFI64X2 ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4134 AVX512F :{EVEX} VSHUFI64X2 zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4135 AVX512VL_VBMI :{EVEX} VPERMB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4136 AVX512VL_VBMI :{EVEX} VPERMB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4137 AVX512_VBMI :{EVEX} VPERMB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4138 AVX512VLBW :{EVEX} VPERMW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4139 AVX512VLBW :{EVEX} VPERMW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4140 AVX512BW :{EVEX} VPERMW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4141 AVX512VL :{EVEX} VPERMD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4142 AVX512F :{EVEX} VPERMD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4143 AVX512VL :{EVEX} VPERMQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4144 AVX512F :{EVEX} VPERMQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4145 AVX512VL :{EVEX} VPERMQ ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4146 AVX512F :{EVEX} VPERMQ zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4147 AVX512VL_VBMI :{EVEX} VPERMI2B xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4148 AVX512VL_VBMI :{EVEX} VPERMI2B ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4149 AVX512_VBMI :{EVEX} VPERMI2B zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4150 AVX512VLBW :{EVEX} VPERMI2W xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4151 AVX512VLBW :{EVEX} VPERMI2W ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4152 AVX512BW :{EVEX} VPERMI2W zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4153 AVX512VL :{EVEX} VPERMI2D xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4154 AVX512VL :{EVEX} VPERMI2D ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4155 AVX512F :{EVEX} VPERMI2D zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4156 AVX512VL :{EVEX} VPERMI2Q xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4157 AVX512VL :{EVEX} VPERMI2Q ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4158 AVX512F :{EVEX} VPERMI2Q zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4159 AVX512VL_VBMI :{EVEX} VPERMT2B xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4160 AVX512VL_VBMI :{EVEX} VPERMT2B ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4161 AVX512_VBMI :{EVEX} VPERMT2B zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4162 AVX512VLBW :{EVEX} VPERMT2W xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4163 AVX512VLBW :{EVEX} VPERMT2W ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4164 AVX512BW :{EVEX} VPERMT2W zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4165 AVX512VL :{EVEX} VPERMT2D xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4166 AVX512VL :{EVEX} VPERMT2D ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4167 AVX512F :{EVEX} VPERMT2D zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4168 AVX512VL :{EVEX} VPERMT2Q xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4169 AVX512VL :{EVEX} VPERMT2Q ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4170 AVX512F :{EVEX} VPERMT2Q zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4171 AVX512VL :{EVEX} VPGATHERDD xmm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4172 AVX512VL :{EVEX} VPGATHERDD ymm {k}, [ym32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4173 AVX512F :{EVEX} VPGATHERDD zmm {k}, [zm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4174 AVX512VL :{EVEX} VPGATHERQD xmm {k}, [xm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4175 AVX512VL :{EVEX} VPGATHERQD xmm {k}, [ym64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4176 AVX512F :{EVEX} VPGATHERQD ymm {k}, [zm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4177 AVX512VL :{EVEX} VPGATHERDQ xmm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4178 AVX512VL :{EVEX} VPGATHERDQ ymm {k}, [xm32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4179 AVX512F :{EVEX} VPGATHERDQ zmm {k}, [ym32] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4180 AVX512VL :{EVEX} VPGATHERQQ xmm {k}, [xm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4181 AVX512VL :{EVEX} VPGATHERQQ ymm {k}, [ym64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4182 AVX512F :{EVEX} VPGATHERQQ zmm {k}, [zm64] + KMOVW L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4183 AVX512VL :{EVEX} VPSCATTERDD [xm32] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4184 AVX512VL :{EVEX} VPSCATTERDD [ym32] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4185 AVX512F :{EVEX} VPSCATTERDD [zm32] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4186 AVX512VL :{EVEX} VPSCATTERQD [xm64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4187 AVX512VL :{EVEX} VPSCATTERQD [ym64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4188 AVX512F :{EVEX} VPSCATTERQD [zm64] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4189 AVX512VL :{EVEX} VPSCATTERDQ [xm32] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4190 AVX512VL :{EVEX} VPSCATTERDQ [xm32] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4191 AVX512F :{EVEX} VPSCATTERDQ [ym32] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4192 AVX512VL :{EVEX} VPSCATTERQQ [xm64] {k}, xmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4193 AVX512VL :{EVEX} VPSCATTERQQ [ym64] {k}, ymm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4194 AVX512F :{EVEX} VPSCATTERQQ [zm64] {k}, zmm + KMOVW L: [memory dep.] T: 0.00ns= 0.000c 4195 AVX :{VEX} VMOVAPS+VEXTRACTF128 [m128], ym, im8 L: [memory dep.] T: 0.00ns= 0.000c 4196 AVX2 :{VEX} VMOVDQA+VEXTRACTI128 [m128], ym, im8 L: [memory dep.] T: 0.00ns= 0.000c 4197 AVX512VL :{EVEX} VMOVAPS+VEXTRACTF32X4 [m128], ym, im8 L: [memory dep.] T: 0.00ns= 0.000c 4198 AVX512F :{EVEX} VMOVAPS+VEXTRACTF32X4 [m128], zm, im8 L: [memory dep.] T: 0.00ns= 0.000c 4199 AVX512DQ :{EVEX} VMOVAPS+VEXTRACTF32X8 [m256], zm, im8 L: [memory dep.] T: 0.00ns= 0.000c 4200 AVX512VLDQ :{EVEX} VMOVAPD+VEXTRACTF64X2 [m128], ym, im8 L: [memory dep.] T: 0.00ns= 0.000c 4201 AVX512DQ :{EVEX} VMOVAPD+VEXTRACTF64X2 [m128], zm, im8 L: [memory dep.] T: 0.00ns= 0.000c 4202 AVX512F :{EVEX} VMOVAPD+VEXTRACTF64X4 [m256], zm, im8 L: [memory dep.] T: 0.00ns= 0.000c 4203 AVX512VL :{EVEX} VMOVDQA32+VEXTRACTI32X4 [m128],ym,im8 L: [memory dep.] T: 0.00ns= 0.000c 4204 AVX512F :{EVEX} VMOVDQA32+VEXTRACTI32X4 [m128],zm,im8 L: [memory dep.] T: 0.00ns= 0.000c 4205 AVX512DQ :{EVEX} VMOVDQA32+VEXTRACTI32X8 [m256],zm,im8 L: [memory dep.] T: 0.00ns= 0.000c 4206 AVX512VLDQ :{EVEX} VMOVDQA64+VEXTRACTI64X2 [m128],ym,im8 L: [memory dep.] T: 0.00ns= 0.000c 4207 AVX512DQ :{EVEX} VMOVDQA64+VEXTRACTI64X2 [m128],zm,im8 L: [memory dep.] T: 0.00ns= 0.000c 4208 AVX512F :{EVEX} VMOVDQA64+VEXTRACTI64X4 [m256],zm,im8 L: [memory dep.] T: 0.00ns= 0.000c 4209 AVX :{VEX} VMOVAPS+VINSERTF128 ym, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4210 AVX2 :{VEX} VMOVDQA+VINSERTI128 ym, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4211 AVX512VL :{EVEX} VMOVAPS+VINSERTF32X4 ym, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4212 AVX512F :{EVEX} VMOVAPS+VINSERTF32X4 zm, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4213 AVX512DQ :{EVEX} VMOVAPS+VINSERTF32X8 zm, [m256], im8 L: [memory dep.] T: 0.00ns= 0.000c 4214 AVX512VLDQ :{EVEX} VMOVAPD+VINSERTF64x2 ym, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4215 AVX512DQ :{EVEX} VMOVAPD+VINSERTF64X4 zm, [m128], im8 L: [memory dep.] T: 0.00ns= 0.000c 4216 AVX512F :{EVEX} VMOVAPD+VINSERTF64X4 zm, [m256], im8 L: [memory dep.] T: 0.00ns= 0.000c 4217 AVX512VL :{EVEX} VMOVDQA32+VINSERTI32X4 ym, [m128],im8 L: [memory dep.] T: 0.00ns= 0.000c 4218 AVX512F :{EVEX} VMOVDQA32+VINSERTI32X4 zm, [m128],im8 L: [memory dep.] T: 0.00ns= 0.000c 4219 AVX512DQ :{EVEX} VMOVDQA32+VINSERTI32X8 zm, [m256],im8 L: [memory dep.] T: 0.00ns= 0.000c 4220 AVX512VLDQ :{EVEX} VMOVDQA64+VINSERTI64x2 ym, [m128],im8 L: [memory dep.] T: 0.00ns= 0.000c 4221 AVX512DQ :{EVEX} VMOVDQA64+VINSERTI64X4 zm, [m128],im8 L: [memory dep.] T: 0.00ns= 0.000c 4222 AVX512F :{EVEX} VMOVDQA64+VINSERTI64X4 zm, [m256],im8 L: [memory dep.] T: 0.00ns= 0.000c 4223 AVX512_4FMAPS :{EVEX} V4FMADDSS xmm, xmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4224 AVX512_4FMAPS :{EVEX} V4FMADDPS zmm, zmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4225 AVX512_4FMAPS :{EVEX} V4FNMADDSS xmm, xmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4226 AVX512_4FMAPS :{EVEX} V4FNMADDPS zmm, zmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4227 AVX512_4VNNIW :{EVEX} VP4DPWSSD zmm, zmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4228 AVX512_4VNNIW :{EVEX} VP4DPWSSDS zmm, zmm+3, [m128] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4229 AVX512VL_VNNI :{EVEX} VPDPBUSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4230 AVX512VL_VNNI :{EVEX} VPDPBUSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4231 AVX512_VNNI :{EVEX} VPDPBUSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4232 AVX512VL_VNNI :{EVEX} VPDPBUSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4233 AVX512VL_VNNI :{EVEX} VPDPBUSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4234 AVX512_VNNI :{EVEX} VPDPBUSDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4235 AVX512VL_VNNI :{EVEX} VPDPWSSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4236 AVX512VL_VNNI :{EVEX} VPDPWSSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4237 AVX512_VNNI :{EVEX} VPDPWSSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4238 AVX512VL_VNNI :{EVEX} VPDPWSSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4239 AVX512VL_VNNI :{EVEX} VPDPWSSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4240 AVX512_VNNI :{EVEX} VPDPWSSDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4241 AVX512VL_BITALG :{EVEX} VPOPCNTB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4242 AVX512VL_BITALG :{EVEX} VPOPCNTB ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4243 AVX512_BITALG :{EVEX} VPOPCNTB zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4244 AVX512VL_BITALG :{EVEX} VPOPCNTW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4245 AVX512VL_BITALG :{EVEX} VPOPCNTW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4246 AVX512_BITALG :{EVEX} VPOPCNTW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4247 AVX512VL_VPOPCNTDQ :{EVEX} VPOPCNTD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4248 AVX512VL_VPOPCNTDQ :{EVEX} VPOPCNTD ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4249 AVX512_VPOPCNTDQ :{EVEX} VPOPCNTD zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4250 AVX512VL_VPOPCNTDQ :{EVEX} VPOPCNTQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4251 AVX512VL_VPOPCNTDQ :{EVEX} VPOPCNTQ ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4252 AVX512_VPOPCNTDQ :{EVEX} VPOPCNTQ zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4253 AVX512VL_BITALG :{EVEX} VPSHUFBITQMB k, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4254 AVX512VL_BITALG :{EVEX} VPSHUFBITQMB k, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 4255 AVX512_BITALG :{EVEX} VPSHUFBITQMB k, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 4256 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4257 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSB ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4258 AVX512_VBMI2 :{EVEX} VPCOMPRESSB zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4259 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4260 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4261 AVX512_VBMI2 :{EVEX} VPCOMPRESSW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4262 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSB xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4263 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSB ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4264 AVX512_VBMI2 :{EVEX} VPCOMPRESSB zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4265 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSW xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4266 AVX512VL_VBMI2 :{EVEX} VPCOMPRESSW ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4267 AVX512_VBMI2 :{EVEX} VPCOMPRESSW zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4268 AVX512VL_VBMI2 :{EVEX} VPEXPANDB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4269 AVX512VL_VBMI2 :{EVEX} VPEXPANDB ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4270 AVX512_VBMI2 :{EVEX} VPEXPANDB zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4271 AVX512VL_VBMI2 :{EVEX} VPEXPANDW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4272 AVX512VL_VBMI2 :{EVEX} VPEXPANDW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4273 AVX512_VBMI2 :{EVEX} VPEXPANDW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4274 AVX512VL_VBMI2 :{EVEX} VPEXPANDB xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4275 AVX512VL_VBMI2 :{EVEX} VPEXPANDB ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4276 AVX512_VBMI2 :{EVEX} VPEXPANDB zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4277 AVX512VL_VBMI2 :{EVEX} VPEXPANDW xmm {k}, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4278 AVX512VL_VBMI2 :{EVEX} VPEXPANDW ymm {k}, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4279 AVX512_VBMI2 :{EVEX} VPEXPANDW zmm {k}, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4280 AVX512VL_VBMI2 :{EVEX} VPSHLDW xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4281 AVX512VL_VBMI2 :{EVEX} VPSHLDW ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4282 AVX512_VBMI2 :{EVEX} VPSHLDW zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4283 AVX512VL_VBMI2 :{EVEX} VPSHLDD xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4284 AVX512VL_VBMI2 :{EVEX} VPSHLDD ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4285 AVX512_VBMI2 :{EVEX} VPSHLDD zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4286 AVX512VL_VBMI2 :{EVEX} VPSHLDQ xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4287 AVX512VL_VBMI2 :{EVEX} VPSHLDQ ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4288 AVX512_VBMI2 :{EVEX} VPSHLDQ zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4289 AVX512VL_VBMI2 :{EVEX} VPSHRDW xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4290 AVX512VL_VBMI2 :{EVEX} VPSHRDW ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4291 AVX512_VBMI2 :{EVEX} VPSHRDW zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4292 AVX512VL_VBMI2 :{EVEX} VPSHRDD xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4293 AVX512VL_VBMI2 :{EVEX} VPSHRDD ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4294 AVX512_VBMI2 :{EVEX} VPSHRDD zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4295 AVX512VL_VBMI2 :{EVEX} VPSHRDQ xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4296 AVX512VL_VBMI2 :{EVEX} VPSHRDQ ymm, ymm, ymm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4297 AVX512_VBMI2 :{EVEX} VPSHRDQ zmm, zmm, zmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4298 AVX512VL_VBMI2 :{EVEX} VPSHLDVW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4299 AVX512VL_VBMI2 :{EVEX} VPSHLDVW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4300 AVX512_VBMI2 :{EVEX} VPSHLDVW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4301 AVX512VL_VBMI2 :{EVEX} VPSHLDVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4302 AVX512VL_VBMI2 :{EVEX} VPSHLDVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4303 AVX512_VBMI2 :{EVEX} VPSHLDVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4304 AVX512VL_VBMI2 :{EVEX} VPSHLDVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4305 AVX512VL_VBMI2 :{EVEX} VPSHLDVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4306 AVX512_VBMI2 :{EVEX} VPSHLDVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4307 AVX512VL_VBMI2 :{EVEX} VPSHRDVW xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4308 AVX512VL_VBMI2 :{EVEX} VPSHRDVW ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4309 AVX512_VBMI2 :{EVEX} VPSHRDVW zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4310 AVX512VL_VBMI2 :{EVEX} VPSHRDVD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4311 AVX512VL_VBMI2 :{EVEX} VPSHRDVD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4312 AVX512_VBMI2 :{EVEX} VPSHRDVD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4313 AVX512VL_VBMI2 :{EVEX} VPSHRDVQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4314 AVX512VL_VBMI2 :{EVEX} VPSHRDVQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4315 AVX512_VBMI2 :{EVEX} VPSHRDVQ zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4316 AVX+VAES :{VEX} VAESDEC ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4317 AVX512VL+VAES :{EVEX} VAESDEC xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4318 AVX512VL+VAES :{EVEX} VAESDEC ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4319 AVX512F+VAES :{EVEX} VAESDEC zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4320 AVX+VAES :{VEX} VAESDECLAST ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4321 AVX512VL+VAES :{EVEX} VAESDECLAST xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4322 AVX512VL+VAES :{EVEX} VAESDECLAST ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4323 AVX512F+VAES :{EVEX} VAESDECLAST zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4324 AVX+VAES :{VEX} VAESENC ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4325 AVX512VL+VAES :{EVEX} VAESENC xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4326 AVX512VL+VAES :{EVEX} VAESENC ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4327 AVX512F+VAES :{EVEX} VAESENC zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4328 AVX+VAES :{VEX} VAESENCLAST ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4329 AVX512VL+VAES :{EVEX} VAESENCLAST xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4330 AVX512VL+VAES :{EVEX} VAESENCLAST ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4331 AVX512F+VAES :{EVEX} VAESENCLAST zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4332 AVX+VPCLMULQDQ :{VEX} VPCLMULQDQ ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4333 AVX512VL+VPCLMULQDQ :{EVEX} VPCLMULQDQ xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4334 AVX512VL+VPCLMULQDQ :{EVEX} VPCLMULQDQ ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4335 AVX512F+VPCLMULQDQ :{EVEX} VPCLMULQDQ zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4336 GFNI :{REX} GF2P8AFFINEINVQB xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4337 AVX+GFNI :{VEX} VGF2P8AFFINEINVQB xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4338 AVX+GFNI :{VEX} VGF2P8AFFINEINVQB ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4339 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEINVQB x, x, x, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4340 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEINVQB y, y, y, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4341 AVX512F+GFNI :{EVEX} VGF2P8AFFINEINVQB zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4342 GFNI :{REX} GF2P8AFFINEQB xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4343 AVX+GFNI :{VEX} VGF2P8AFFINEQB xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4344 AVX+GFNI :{VEX} VGF2P8AFFINEQB ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4345 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB xm, xm, xm, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4346 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB ym, ym, ym, im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4347 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4348 GFNI :{REX} GF2P8MULB xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4349 AVX+GFNI :{VEX} VGF2P8MULB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4350 AVX+GFNI :{VEX} VGF2P8MULB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4351 AVX512VL+GFNI :{EVEX} VGF2P8MULB xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4352 AVX512VL+GFNI :{EVEX} VGF2P8MULB ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4353 AVX512F+GFNI :{EVEX} VGF2P8MULB zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4354 X86 :{REX} SHLD r1_16, r2_16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4355 X86 :{REX} SHLD r1_32, r2_32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4356 AMD64 :{REX} SHLD r1_64, r2_64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4357 X86 :{REX} SHLD r1_16, r2_16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4358 X86 :{REX} SHLD r1_32, r2_32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4359 AMD64 :{REX} SHLD r1_64, r2_64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4360 X86 :{REX} SHRD r1_16, r2_16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4361 X86 :{REX} SHRD r1_32, r2_32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4362 AMD64 :{REX} SHRD r1_64, r2_64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4363 X86 :{REX} SHRD r1_16, r2_16, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4364 X86 :{REX} SHRD r1_32, r2_32, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4365 AMD64 :{REX} SHRD r1_64, r2_64, cl L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4366 X86 :{REX} ADC r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4367 X86 :{REX} ADC r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4368 X86 :{REX} ADC r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4369 AMD64 :{REX} ADC r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4370 X86 :{REX} ADC r16, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4371 X86 :{REX} ADC r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4372 AMD64 :{REX} ADC r64, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4373 X86 :{REX} ADC al, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4374 X86 :{REX} ADC ax, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4375 X86 :{REX} ADC eax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4376 AMD64 :{REX} ADC rax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4377 X86 :{REX} ADC r8, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4378 X86 :{REX} ADC r16, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4379 X86 :{REX} ADC r32, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4380 AMD64 :{REX} ADC r64, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4381 X86 :{REX} ADC r16, imm16_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4382 X86 :{REX} ADC r32, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4383 AMD64 :{REX} ADC r64, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4384 X86 :{REX} ADC al, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4385 X86 :{REX} ADC ax, imm16_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4386 X86 :{REX} ADC eax, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4387 AMD64 :{REX} ADC rax, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4388 X86 :{REX} SBB r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4389 X86 :{REX} SBB r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4390 X86 :{REX} SBB r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4391 AMD64 :{REX} SBB r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4392 X86 :{REX} SBB r16, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4393 X86 :{REX} SBB r32, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4394 AMD64 :{REX} SBB r64, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4395 X86 :{REX} SBB al, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4396 X86 :{REX} SBB ax, imm16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4397 X86 :{REX} SBB eax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4398 AMD64 :{REX} SBB rax, imm32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4399 X86 :{REX} SBB r8, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4400 X86 :{REX} SBB r16, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4401 X86 :{REX} SBB r32, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4402 AMD64 :{REX} SBB r64, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4403 X86 :{REX} SBB r16, imm16_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4404 X86 :{REX} SBB r32, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4405 AMD64 :{REX} SBB r64, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4406 X86 :{REX} SBB al, imm8_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4407 X86 :{REX} SBB ax, imm16_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4408 X86 :{REX} SBB eax, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4409 AMD64 :{REX} SBB rax, imm32_0 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4410 AMD64 :{REX} LEA r16, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4411 AMD64 :{REX} LEA r32, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4412 AMD64 :{REX} LEA r64, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4413 AMD64 :{REX} LEA r16, [r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4414 AMD64 :{REX} LEA r32, [r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4415 AMD64 :{REX} LEA r64, [r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4416 AMD64 :{REX} LEA r16, [r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4417 AMD64 :{REX} LEA r32, [r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4418 AMD64 :{REX} LEA r64, [r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4419 AMD64 :{REX} LEA r16, [r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4420 AMD64 :{REX} LEA r32, [r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4421 AMD64 :{REX} LEA r64, [r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4422 AMD64 :{REX} LEA r16, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4423 AMD64 :{REX} LEA r32, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4424 AMD64 :{REX} LEA r64, [r64 + r64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4425 AMD64 :{REX} LEA r16, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4426 AMD64 :{REX} LEA r32, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4427 AMD64 :{REX} LEA r64, [r64 + r64 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4428 AMD64 :{REX} LEA r16, [r64 + r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4429 AMD64 :{REX} LEA r32, [r64 + r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4430 AMD64 :{REX} LEA r64, [r64 + r64 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4431 AMD64 :{REX} LEA r16, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4432 AMD64 :{REX} LEA r32, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4433 AMD64 :{REX} LEA r64, [r64 + r64 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4434 AMD64 :{REX} LEA r16, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4435 AMD64 :{REX} LEA r32, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4436 AMD64 :{REX} LEA r64, [r64 + r64 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4437 AMD64 :{REX} LEA r16, [r64 + r64 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4438 AMD64 :{REX} LEA r32, [r64 + r64 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4439 AMD64 :{REX} LEA r64, [r64 + r64 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4440 AMD64 :{REX} ASP LEA r16, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4441 AMD64 :{REX} ASP LEA r32, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4442 AMD64 :{REX} ASP LEA r64, [disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4443 AMD64 :{REX} ASP LEA r16, [r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4444 AMD64 :{REX} ASP LEA r32, [r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4445 AMD64 :{REX} ASP LEA r64, [r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4446 AMD64 :{REX} ASP LEA r16, [r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4447 AMD64 :{REX} ASP LEA r32, [r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4448 AMD64 :{REX} ASP LEA r64, [r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4449 AMD64 :{REX} ASP LEA r16, [r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4450 AMD64 :{REX} ASP LEA r32, [r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4451 AMD64 :{REX} ASP LEA r64, [r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4452 AMD64 :{REX} ASP LEA r16, [r32 + r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4453 AMD64 :{REX} ASP LEA r32, [r32 + r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4454 AMD64 :{REX} ASP LEA r64, [r32 + r32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4455 AMD64 :{REX} ASP LEA r16, [r32 + r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4456 AMD64 :{REX} ASP LEA r32, [r32 + r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4457 AMD64 :{REX} ASP LEA r64, [r32 + r32 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4458 AMD64 :{REX} ASP LEA r16, [r32 + r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4459 AMD64 :{REX} ASP LEA r32, [r32 + r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4460 AMD64 :{REX} ASP LEA r64, [r32 + r32 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4461 AMD64 :{REX} ASP LEA r16, [r32 + r32 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4462 AMD64 :{REX} ASP LEA r32, [r32 + r32 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4463 AMD64 :{REX} ASP LEA r64, [r32 + r32 * 8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4464 AMD64 :{REX} ASP LEA r16, [r32 + r32 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4465 AMD64 :{REX} ASP LEA r32, [r32 + r32 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4466 AMD64 :{REX} ASP LEA r64, [r32 + r32 * 8 + disp8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4467 AMD64 :{REX} ASP LEA r16, [r32 + r32 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4468 AMD64 :{REX} ASP LEA r32, [r32 + r32 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4469 AMD64 :{REX} ASP LEA r64, [r32 + r32 * 8 + disp32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4470 AVX512VL_BF16 :{EVEX} VCVTNEPS2BF16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4471 AVX512VL_BF16 :{EVEX} VCVTNEPS2BF16 xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4472 AVX512_BF16 :{EVEX} VCVTNEPS2BF16 ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4473 AVX512VL_BF16 :{EVEX} VCVTNE2PS2BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4474 AVX512VL_BF16 :{EVEX} VCVTNE2PS2BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4475 AVX512_BF16 :{EVEX} VCVTNE2PS2BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4476 AVX512VL_BF16 :{EVEX} VDPBF16PS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4477 AVX512VL_BF16 :{EVEX} VDPBF16PS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4478 AVX512_BF16 :{EVEX} VDPBF16PS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4479 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD k1+1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4480 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD k1+1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 4481 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTD k1+1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 4482 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ k1+1, xmm, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4483 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ k1+1, ymm, ymm L: [diff. reg. set] T: 0.00ns= 0.000c 4484 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTQ k1+1, zmm, zmm L: [diff. reg. set] T: 0.00ns= 0.000c 4485 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD + VPMOVM2D xmm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4486 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD + VPMOVM2D xmm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4487 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD + VPMOVM2D ymm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4488 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTD + VPMOVM2D ymm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4489 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTD + VPMOVM2D zmm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4490 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTD + VPMOVM2D zmm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4491 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ + VPMOVM2Q xmm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4492 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ + VPMOVM2Q xmm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4493 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ + VPMOVM2Q ymm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4494 AVX512VL_VP2INTERSE :{EVEX} VP2INTERSECTQ + VPMOVM2Q ymm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4495 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTQ + VPMOVM2Q zmm low L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4496 AVX512_VP2INTERSECT :{EVEX} VP2INTERSECTQ + VPMOVM2Q zmm high L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4497 RDPRU : RDPRU L: [no true dep.] T: 0.00ns= 0.000c 4498 MCOMMIT : MCOMMIT L: [no true dep.] T: 0.00ns= 0.000c 4499 CLDEMOTE :{REX} CLDEMOTE [mem] L: [memory dep.] T: 0.00ns= 0.000c 4500 MOVDIRI :{REX} MOVDIRI [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 4501 MOVDIRI_X64 :{REX} MOVDIRI [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 4502 MOVDIR64B :{REX} MOVDIR64B r64, [m512] L: [memory dep.] T: 0.00ns= 0.000c 4503 WAITPKG :{REX} TPAUSE r32, , L: [no true dep.] T: 0.00ns= 0.000c 4504 WAITPKG :{REX} UMONITOR r32 L: [no true dep.] T: 0.00ns= 0.000c 4505 WAITPKG :{REX} UMWAIT r32, , L: [no true dep.] T: 0.00ns= 0.000c 4506 SERIALIZE : SERIALIZE L: [no true dep.] T: 0.00ns= 0.000c 4507 TSXLDTRK : XSUSLDTRK L: [no true dep.] T: 0.00ns= 0.000c 4508 TSXLDTRK : XRESLDTRK L: [no true dep.] T: 0.00ns= 0.000c 4509 AVX512VLBW :{EVEX} VPADDB xmm{k}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4510 AVX512VLBW :{EVEX} VPADDB ymm{k}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4511 AVX512BW :{EVEX} VPADDB zmm{k}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4512 AVX512VLBW :{EVEX} VPADDW xmm{k}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4513 AVX512VLBW :{EVEX} VPADDW ymm{k}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4514 AVX512BW :{EVEX} VPADDW zmm{k}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4515 AVX512VL :{EVEX} VPADDD xmm{k}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4516 AVX512VL :{EVEX} VPADDD ymm{k}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4517 AVX512F :{EVEX} VPADDD zmm{k}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4518 AVX512VL :{EVEX} VPADDQ xmm{k}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4519 AVX512VL :{EVEX} VPADDQ ymm{k}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4520 AVX512F :{EVEX} VPADDQ zmm{k}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4521 AVX512VLBW :{EVEX} VDBPSADBW xmm{k}, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4522 AVX512VLBW :{EVEX} VDBPSADBW ymm{k}, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4523 AVX512BW :{EVEX} VDBPSADBW zmm{k}, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4524 AVX512VLBW :{EVEX} VPMADDUBSW xmm{k}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4525 AVX512VLBW :{EVEX} VPMADDUBSW ymm{k}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4526 AVX512BW :{EVEX} VPMADDUBSW zmm{k}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4527 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB xm{k},xm,xm,im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4528 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB ym{k},ym,ym,im8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4529 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB zmm{k}, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4530 GFNI :{REX} GF2P8AFFINEQB + PADDB xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4531 AVX+GFNI :{VEX} VGF2P8AFFINEQB + VPADDB xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4532 AVX+GFNI :{VEX} VGF2P8AFFINEQB + VPADDB ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4533 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4534 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4535 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4536 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB xmm{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4537 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB ymm{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4538 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB + VPADDB zmm{k} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4539 AVX_VNNI :{VEX} VPDPBUSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4540 AVX_VNNI :{VEX} VPDPBUSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4541 AVX_VNNI :{VEX} VPDPBUSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4542 AVX_VNNI :{VEX} VPDPBUSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4543 AVX_VNNI :{VEX} VPDPWSSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4544 AVX_VNNI :{VEX} VPDPWSSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4545 AVX_VNNI :{VEX} VPDPWSSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4546 AVX_VNNI :{VEX} VPDPWSSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4547 AVX512_FP16 :{EVEX} VADDSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4548 AVX512VL_FP16 :{EVEX} VADDPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4549 AVX512VL_FP16 :{EVEX} VADDPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4550 AVX512_FP16 :{EVEX} VADDPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4551 AVX512_FP16 :{EVEX} VSUBSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4552 AVX512VL_FP16 :{EVEX} VSUBPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4553 AVX512VL_FP16 :{EVEX} VSUBPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4554 AVX512_FP16 :{EVEX} VSUBPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4555 AVX512_FP16 :{EVEX} VMULSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4556 AVX512VL_FP16 :{EVEX} VMULPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4557 AVX512VL_FP16 :{EVEX} VMULPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4558 AVX512_FP16 :{EVEX} VMULPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4559 AVX512_FP16 :{EVEX} VFCMULCSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4560 AVX512VL_FP16 :{EVEX} VFCMULCPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4561 AVX512VL_FP16 :{EVEX} VFCMULCPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4562 AVX512_FP16 :{EVEX} VFCMULCPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4563 AVX512_FP16 :{EVEX} VFMULCSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4564 AVX512VL_FP16 :{EVEX} VFMULCPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4565 AVX512VL_FP16 :{EVEX} VFMULCPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4566 AVX512_FP16 :{EVEX} VFMULCPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4567 AVX512_FP16 :{EVEX} VFMADD132SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4568 AVX512VL_FP16 :{EVEX} VFMADD132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4569 AVX512VL_FP16 :{EVEX} VFMADD132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4570 AVX512_FP16 :{EVEX} VFMADD132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4571 AVX512_FP16 :{EVEX} VFMADD213SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4572 AVX512VL_FP16 :{EVEX} VFMADD213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4573 AVX512VL_FP16 :{EVEX} VFMADD213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4574 AVX512_FP16 :{EVEX} VFMADD213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4575 AVX512_FP16 :{EVEX} VFMADD231SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4576 AVX512VL_FP16 :{EVEX} VFMADD231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4577 AVX512VL_FP16 :{EVEX} VFMADD231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4578 AVX512_FP16 :{EVEX} VFMADD231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4579 AVX512_FP16 :{EVEX} VFMSUB132SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4580 AVX512VL_FP16 :{EVEX} VFMSUB132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4581 AVX512VL_FP16 :{EVEX} VFMSUB132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4582 AVX512_FP16 :{EVEX} VFMSUB132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4583 AVX512_FP16 :{EVEX} VFMSUB213SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4584 AVX512VL_FP16 :{EVEX} VFMSUB213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4585 AVX512VL_FP16 :{EVEX} VFMSUB213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4586 AVX512_FP16 :{EVEX} VFMSUB213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4587 AVX512_FP16 :{EVEX} VFMSUB231SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4588 AVX512VL_FP16 :{EVEX} VFMSUB231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4589 AVX512VL_FP16 :{EVEX} VFMSUB231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4590 AVX512_FP16 :{EVEX} VFMSUB231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4591 AVX512_FP16 :{EVEX} VFNMADD132SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4592 AVX512VL_FP16 :{EVEX} VFNMADD132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4593 AVX512VL_FP16 :{EVEX} VFNMADD132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4594 AVX512_FP16 :{EVEX} VFNMADD132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4595 AVX512_FP16 :{EVEX} VFNMADD213SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4596 AVX512VL_FP16 :{EVEX} VFNMADD213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4597 AVX512VL_FP16 :{EVEX} VFNMADD213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4598 AVX512_FP16 :{EVEX} VFNMADD213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4599 AVX512_FP16 :{EVEX} VFNMADD231SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4600 AVX512VL_FP16 :{EVEX} VFNMADD231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4601 AVX512VL_FP16 :{EVEX} VFNMADD231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4602 AVX512_FP16 :{EVEX} VFNMADD231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4603 AVX512_FP16 :{EVEX} VFNMSUB132SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4604 AVX512VL_FP16 :{EVEX} VFNMSUB132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4605 AVX512VL_FP16 :{EVEX} VFNMSUB132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4606 AVX512_FP16 :{EVEX} VFNMSUB132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4607 AVX512_FP16 :{EVEX} VFNMSUB213SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4608 AVX512VL_FP16 :{EVEX} VFNMSUB213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4609 AVX512VL_FP16 :{EVEX} VFNMSUB213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4610 AVX512_FP16 :{EVEX} VFNMSUB213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4611 AVX512_FP16 :{EVEX} VFNMSUB231SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4612 AVX512VL_FP16 :{EVEX} VFNMSUB231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4613 AVX512VL_FP16 :{EVEX} VFNMSUB231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4614 AVX512_FP16 :{EVEX} VFNMSUB231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4615 AVX512VL_FP16 :{EVEX} VFMADDSUB132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4616 AVX512VL_FP16 :{EVEX} VFMADDSUB132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4617 AVX512_FP16 :{EVEX} VFMADDSUB132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4618 AVX512VL_FP16 :{EVEX} VFMADDSUB213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4619 AVX512VL_FP16 :{EVEX} VFMADDSUB213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4620 AVX512_FP16 :{EVEX} VFMADDSUB213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4621 AVX512VL_FP16 :{EVEX} VFMADDSUB231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4622 AVX512VL_FP16 :{EVEX} VFMADDSUB231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4623 AVX512_FP16 :{EVEX} VFMADDSUB231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4624 AVX512VL_FP16 :{EVEX} VFMSUBADD132PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4625 AVX512VL_FP16 :{EVEX} VFMSUBADD132PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4626 AVX512_FP16 :{EVEX} VFMSUBADD132PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4627 AVX512VL_FP16 :{EVEX} VFMSUBADD213PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4628 AVX512VL_FP16 :{EVEX} VFMSUBADD213PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4629 AVX512_FP16 :{EVEX} VFMSUBADD213PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4630 AVX512VL_FP16 :{EVEX} VFMSUBADD231PH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4631 AVX512VL_FP16 :{EVEX} VFMSUBADD231PH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4632 AVX512_FP16 :{EVEX} VFMSUBADD231PH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4633 AVX512_FP16 :{EVEX} VFCMADDCSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4634 AVX512VL_FP16 :{EVEX} VFCMADDCPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4635 AVX512VL_FP16 :{EVEX} VFCMADDCPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4636 AVX512_FP16 :{EVEX} VFCMADDCPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4637 AVX512_FP16 :{EVEX} VFMADDCSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4638 AVX512VL_FP16 :{EVEX} VFMADDCPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4639 AVX512VL_FP16 :{EVEX} VFMADDCPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4640 AVX512_FP16 :{EVEX} VFMADDCPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4641 AVX512_FP16 :{EVEX} VDIVSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4642 AVX512_FP16 :{EVEX} VDIVSH xmm (0.0f16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4643 AVX512_FP16 :{EVEX} VDIVSH xmm (x/1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4644 AVX512_FP16 :{EVEX} VDIVSH xmm (x/2.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4645 AVX512_FP16 :{EVEX} VDIVSH xmm (x/0.5f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4646 AVX512VL_FP16 :{EVEX} VDIVPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4647 AVX512VL_FP16 :{EVEX} VDIVPH xmm (0.0f16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4648 AVX512VL_FP16 :{EVEX} VDIVPH xmm (x/1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4649 AVX512VL_FP16 :{EVEX} VDIVPH xmm (x/2.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4650 AVX512VL_FP16 :{EVEX} VDIVPH xmm (x/0.5f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4651 AVX512VL_FP16 :{EVEX} VDIVPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4652 AVX512VL_FP16 :{EVEX} VDIVPH ymm (0.0f16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4653 AVX512VL_FP16 :{EVEX} VDIVPH ymm (x/1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4654 AVX512VL_FP16 :{EVEX} VDIVPH ymm (x/2.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4655 AVX512VL_FP16 :{EVEX} VDIVPH ymm (x/0.5f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4656 AVX512_FP16 :{EVEX} VDIVPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4657 AVX512_FP16 :{EVEX} VDIVPH zmm (0.0f16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4658 AVX512_FP16 :{EVEX} VDIVPH zmm (x/1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4659 AVX512_FP16 :{EVEX} VDIVPH zmm (x/2.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4660 AVX512_FP16 :{EVEX} VDIVPH zmm (x/0.5f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4661 AVX512_FP16 :{EVEX} VSQRTSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4662 AVX512_FP16 :{EVEX} VSQRTSH xmm, (0.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4663 AVX512_FP16 :{EVEX} VSQRTSH xmm, (1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4664 AVX512VL_FP16 :{EVEX} VSQRTPH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4665 AVX512VL_FP16 :{EVEX} VSQRTPH xmm (0.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4666 AVX512VL_FP16 :{EVEX} VSQRTPH xmm (1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4667 AVX512VL_FP16 :{EVEX} VSQRTPH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4668 AVX512VL_FP16 :{EVEX} VSQRTPH ymm (0.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4669 AVX512VL_FP16 :{EVEX} VSQRTPH ymm (1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4670 AVX512_FP16 :{EVEX} VSQRTPH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4671 AVX512_FP16 :{EVEX} VSQRTPH zmm (0.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4672 AVX512_FP16 :{EVEX} VSQRTPH zmm (1.0f16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4673 AVX512_FP16 :{EVEX} VRCPSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4674 AVX512VL_FP16 :{EVEX} VRCPPH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4675 AVX512VL_FP16 :{EVEX} VRCPPH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4676 AVX512_FP16 :{EVEX} VRCPPH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4677 AVX512_FP16 :{EVEX} VRSQRTSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4678 AVX512VL_FP16 :{EVEX} VRSQRTPH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4679 AVX512VL_FP16 :{EVEX} VRSQRTPH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4680 AVX512_FP16 :{EVEX} VRSQRTPH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4681 AVX512_FP16 :{EVEX} VMINSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4682 AVX512VL_FP16 :{EVEX} VMINPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4683 AVX512VL_FP16 :{EVEX} VMINPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4684 AVX512_FP16 :{EVEX} VMINPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4685 AVX512_FP16 :{EVEX} VMAXSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4686 AVX512VL_FP16 :{EVEX} VMAXPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4687 AVX512VL_FP16 :{EVEX} VMAXPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4688 AVX512_FP16 :{EVEX} VMAXPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4689 AVX512_FP16 :{EVEX} VCMPSH k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4690 AVX512VL_FP16 :{EVEX} VCMPPH k1, xmm, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4691 AVX512VL_FP16 :{EVEX} VCMPPH k1, ymm, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4692 AVX512_FP16 :{EVEX} VCMPPH k1, zmm, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4693 AVX512_FP16 :{EVEX} VCOMISH xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 4694 AVX512_FP16 :{EVEX} VUCOMISH xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 4695 AVX512_FP16 :{EVEX} VCVTSS2SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4696 AVX512VL_FP16 :{EVEX} VCVTPS2PHX xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4697 AVX512VL_FP16 :{EVEX} VCVTPS2PHX xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4698 AVX512_FP16 :{EVEX} VCVTPS2PHX ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4699 AVX512_FP16 :{EVEX} VCVTSH2SS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4700 AVX512VL_FP16 :{EVEX} VCVTPH2PSX xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4701 AVX512VL_FP16 :{EVEX} VCVTPH2PSX ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4702 AVX512_FP16 :{EVEX} VCVTPH2PSX zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4703 AVX512_FP16 :{EVEX} VCVTSS2SH + VCVTSH2SS xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4704 AVX512VL_FP16 :{EVEX} VCVTPS2PHX + VCVTPH2PSX xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4705 AVX512VL_FP16 :{EVEX} VCVTPS2PHX + VCVTPH2PSX ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4706 AVX512_FP16 :{EVEX} VCVTPS2PHX + VCVTPH2PSX zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4707 AVX512_FP16 :{EVEX} VCVTSD2SH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4708 AVX512VL_FP16 :{EVEX} VCVTPD2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4709 AVX512VL_FP16 :{EVEX} VCVTPD2PH xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4710 AVX512_FP16 :{EVEX} VCVTPD2PH xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4711 AVX512_FP16 :{EVEX} VCVTSH2SD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4712 AVX512VL_FP16 :{EVEX} VCVTPH2PD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4713 AVX512VL_FP16 :{EVEX} VCVTPH2PD ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4714 AVX512_FP16 :{EVEX} VCVTPH2PD zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4715 AVX512_FP16 :{EVEX} VCVTSD2SH + VCVTSH2SD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4716 AVX512VL_FP16 :{EVEX} VCVTPD2PH + VCVTPH2PD xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4717 AVX512VL_FP16 :{EVEX} VCVTPD2PH + VCVTPH2PD ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4718 AVX512_FP16 :{EVEX} VCVTPD2PH + VCVTPH2PD zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4719 AVX512VL_FP16 :{EVEX} VCVTW2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4720 AVX512VL_FP16 :{EVEX} VCVTW2PH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4721 AVX512_FP16 :{EVEX} VCVTW2PH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4722 AVX512VL_FP16 :{EVEX} VCVTUW2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4723 AVX512VL_FP16 :{EVEX} VCVTUW2PH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4724 AVX512_FP16 :{EVEX} VCVTUW2PH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4725 AVX512VL_FP16 :{EVEX} VCVTPH2W xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4726 AVX512VL_FP16 :{EVEX} VCVTPH2W ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4727 AVX512_FP16 :{EVEX} VCVTPH2W zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4728 AVX512VL_FP16 :{EVEX} VCVTPH2UW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4729 AVX512VL_FP16 :{EVEX} VCVTPH2UW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4730 AVX512_FP16 :{EVEX} VCVTPH2UW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4731 AVX512VL_FP16 :{EVEX} VCVTTPH2W xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4732 AVX512VL_FP16 :{EVEX} VCVTTPH2W ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4733 AVX512_FP16 :{EVEX} VCVTTPH2W zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4734 AVX512VL_FP16 :{EVEX} VCVTTPH2UW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4735 AVX512VL_FP16 :{EVEX} VCVTTPH2UW ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4736 AVX512_FP16 :{EVEX} VCVTTPH2UW zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4737 AVX512VL_FP16 :{EVEX} VCVTW2PH + VCVTPH2W xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4738 AVX512VL_FP16 :{EVEX} VCVTW2PH + VCVTPH2W ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4739 AVX512_FP16 :{EVEX} VCVTW2PH + VCVTPH2W zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4740 AVX512VL_FP16 :{EVEX} VCVTUW2PH + VCVTPH2UW xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4741 AVX512VL_FP16 :{EVEX} VCVTUW2PH + VCVTPH2UW ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4742 AVX512_FP16 :{EVEX} VCVTUW2PH + VCVTPH2UW zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4743 AVX512VL_FP16 :{EVEX} VCVTW2PH + VCVTTPH2W xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4744 AVX512VL_FP16 :{EVEX} VCVTW2PH + VCVTTPH2W ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4745 AVX512_FP16 :{EVEX} VCVTW2PH + VCVTTPH2W zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4746 AVX512VL_FP16 :{EVEX} VCVTUW2PH + VCVTTPH2UW xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4747 AVX512VL_FP16 :{EVEX} VCVTUW2PH + VCVTTPH2UW ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4748 AVX512_FP16 :{EVEX} VCVTUW2PH + VCVTTPH2UW zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4749 AVX512VL_FP16 :{EVEX} VCVTDQ2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4750 AVX512VL_FP16 :{EVEX} VCVTDQ2PH xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4751 AVX512_FP16 :{EVEX} VCVTDQ2PH xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4752 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4753 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4754 AVX512_FP16 :{EVEX} VCVTUDQ2PH xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4755 AVX512VL_FP16 :{EVEX} VCVTPH2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4756 AVX512VL_FP16 :{EVEX} VCVTPH2DQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4757 AVX512_FP16 :{EVEX} VCVTPH2DQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4758 AVX512VL_FP16 :{EVEX} VCVTPH2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4759 AVX512VL_FP16 :{EVEX} VCVTPH2UDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4760 AVX512_FP16 :{EVEX} VCVTPH2UDQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4761 AVX512VL_FP16 :{EVEX} VCVTTPH2DQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4762 AVX512VL_FP16 :{EVEX} VCVTTPH2DQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4763 AVX512_FP16 :{EVEX} VCVTTPH2DQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4764 AVX512VL_FP16 :{EVEX} VCVTTPH2UDQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4765 AVX512VL_FP16 :{EVEX} VCVTTPH2UDQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4766 AVX512_FP16 :{EVEX} VCVTTPH2UDQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4767 AVX512VL_FP16 :{EVEX} VCVTDQ2PH + VCVTPH2DQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4768 AVX512VL_FP16 :{EVEX} VCVTDQ2PH + VCVTPH2DQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4769 AVX512_FP16 :{EVEX} VCVTDQ2PH + VCVTPH2DQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4770 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH + VCVTPH2UDQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4771 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH + VCVTPH2UDQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4772 AVX512_FP16 :{EVEX} VCVTUDQ2PH + VCVTPH2UDQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4773 AVX512VL_FP16 :{EVEX} VCVTDQ2PH + VCVTTPH2DQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4774 AVX512VL_FP16 :{EVEX} VCVTDQ2PH + VCVTTPH2DQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4775 AVX512_FP16 :{EVEX} VCVTDQ2PH + VCVTTPH2DQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4776 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH + VCVTTPH2UDQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4777 AVX512VL_FP16 :{EVEX} VCVTUDQ2PH + VCVTTPH2UDQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4778 AVX512_FP16 :{EVEX} VCVTUDQ2PH + VCVTTPH2UDQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4779 AVX512VL_FP16 :{EVEX} VCVTQQ2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4780 AVX512VL_FP16 :{EVEX} VCVTQQ2PH xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4781 AVX512_FP16 :{EVEX} VCVTQQ2PH xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4782 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4783 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4784 AVX512_FP16 :{EVEX} VCVTUQQ2PH xmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4785 AVX512VL_FP16 :{EVEX} VCVTPH2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4786 AVX512VL_FP16 :{EVEX} VCVTPH2QQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4787 AVX512_FP16 :{EVEX} VCVTPH2QQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4788 AVX512VL_FP16 :{EVEX} VCVTPH2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4789 AVX512VL_FP16 :{EVEX} VCVTPH2UQQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4790 AVX512_FP16 :{EVEX} VCVTPH2UQQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4791 AVX512VL_FP16 :{EVEX} VCVTTPH2QQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4792 AVX512VL_FP16 :{EVEX} VCVTTPH2QQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4793 AVX512_FP16 :{EVEX} VCVTTPH2QQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4794 AVX512VL_FP16 :{EVEX} VCVTTPH2UQQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4795 AVX512VL_FP16 :{EVEX} VCVTTPH2UQQ ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4796 AVX512_FP16 :{EVEX} VCVTTPH2UQQ zmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4797 AVX512VL_FP16 :{EVEX} VCVTQQ2PH + VCVTPH2QQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4798 AVX512VL_FP16 :{EVEX} VCVTQQ2PH + VCVTPH2QQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4799 AVX512_FP16 :{EVEX} VCVTQQ2PH + VCVTPH2QQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4800 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH + VCVTPH2UQQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4801 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH + VCVTPH2UQQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4802 AVX512_FP16 :{EVEX} VCVTUQQ2PH + VCVTPH2UQQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4803 AVX512VL_FP16 :{EVEX} VCVTQQ2PH + VCVTTPH2QQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4804 AVX512VL_FP16 :{EVEX} VCVTQQ2PH + VCVTTPH2QQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4805 AVX512_FP16 :{EVEX} VCVTQQ2PH + VCVTTPH2QQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4806 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH + VCVTTPH2UQQ xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4807 AVX512VL_FP16 :{EVEX} VCVTUQQ2PH + VCVTTPH2UQQ ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4808 AVX512_FP16 :{EVEX} VCVTUQQ2PH + VCVTTPH2UQQ zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4809 AVX512_FP16 :{EVEX} VCVTSH2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4810 AVX512_FP16_X64 :{EVEX} VCVTSH2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4811 AVX512_FP16 :{EVEX} VCVTSH2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4812 AVX512_FP16_X64 :{EVEX} VCVTSH2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4813 AVX512_FP16 :{EVEX} VCVTTSH2SI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4814 AVX512_FP16_X64 :{EVEX} VCVTTSH2SI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4815 AVX512_FP16 :{EVEX} VCVTTSH2USI r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4816 AVX512_FP16_X64 :{EVEX} VCVTTSH2USI r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4817 AVX512_FP16 :{EVEX} VCVTSI2SH xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 4818 AVX512_FP16_X64 :{EVEX} VCVTSI2SH xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 4819 AVX512_FP16 :{EVEX} VCVTUSI2SH xmm, xmm, r32 L: [diff. reg. set] T: 0.00ns= 0.000c 4820 AVX512_FP16_X64 :{EVEX} VCVTUSI2SH xmm, xmm, r64 L: [diff. reg. set] T: 0.00ns= 0.000c 4821 AVX512_FP16 :{EVEX} VCVTSH2SI + VCVTSI2SH r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4822 AVX512_FP16_X64 :{EVEX} VCVTSH2SI + VCVTSI2SH r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4823 AVX512_FP16 :{EVEX} VCVTSH2USI + VCVTUSI2SH r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4824 AVX512_FP16_X64 :{EVEX} VCVTSH2USI + VCVTUSI2SH r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4825 AVX512_FP16 :{EVEX} VCVTTSH2SI + VCVTSI2SH r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4826 AVX512_FP16_X64 :{EVEX} VCVTTSH2SI + VCVTSI2SH r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4827 AVX512_FP16 :{EVEX} VCVTTSH2USI + VCVTUSI2SH r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4828 AVX512_FP16_X64 :{EVEX} VCVTTSH2USI + VCVTUSI2SH r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4829 AVX512_FP16 :{EVEX} VFPCLASSSH k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4830 AVX512VL_FP16 :{EVEX} VFPCLASSPH k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4831 AVX512VL_FP16 :{EVEX} VFPCLASSPH k, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4832 AVX512_FP16 :{EVEX} VFPCLASSPH k, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 4833 AVX512_FP16 :{EVEX} VGETEXPSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4834 AVX512VL_FP16 :{EVEX} VGETEXPPH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4835 AVX512VL_FP16 :{EVEX} VGETEXPPH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4836 AVX512_FP16 :{EVEX} VGETEXPPH zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4837 AVX512_FP16 :{EVEX} VGETMANTSH xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4838 AVX512VL_FP16 :{EVEX} VGETMANTPH xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4839 AVX512VL_FP16 :{EVEX} VGETMANTPH ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4840 AVX512_FP16 :{EVEX} VGETMANTPH zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4841 AVX512_FP16 :{EVEX} VREDUCESH xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4842 AVX512VL_FP16 :{EVEX} VREDUCEPH xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4843 AVX512VL_FP16 :{EVEX} VREDUCEPH ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4844 AVX512_FP16 :{EVEX} VREDUCEPH zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4845 AVX512_FP16 :{EVEX} VRNDSCALESH xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4846 AVX512VL_FP16 :{EVEX} VRNDSCALEPH xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4847 AVX512VL_FP16 :{EVEX} VRNDSCALEPH ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4848 AVX512_FP16 :{EVEX} VRNDSCALEPH zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4849 AVX512_FP16 :{EVEX} VSCALEFSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4850 AVX512VL_FP16 :{EVEX} VSCALEFPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4851 AVX512VL_FP16 :{EVEX} VSCALEFPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4852 AVX512_FP16 :{EVEX} VSCALEFPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4853 AVX512_FP16 :{EVEX} VMOVSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4854 AVX512_FP16 :{EVEX} VMOVSH xmm1, xmm2, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4855 AVX512_FP16 :{EVEX} VMOVSH xmm, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4856 AVX512_FP16 :{EVEX} VMOVSH [m16], xmm L: [memory dep.] T: 0.00ns= 0.000c 4857 AVX512_FP16 :{EVEX} VMOVSH LS pair L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4858 AVX512_FP16 :{EVEX} VMOVW r16, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 4859 AVX512_FP16 :{EVEX} VMOVW xmm, r16 L: [diff. reg. set] T: 0.00ns= 0.000c 4860 AVX512_FP16 :{EVEX} VMOVW r16, xmm + xmm, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4861 AVX512_FP16 :{EVEX} VMOVW xmm, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4862 AVX512_FP16 :{EVEX} VMOVW [m16], xmm L: [memory dep.] T: 0.00ns= 0.000c 4863 AVX512_FP16 :{EVEX} VMOVW xmm, [m16] + [m16], xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4864 AMX-BF16 :{VEX} TDPBF16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4865 AMX-INT8 :{VEX} TDPBSSD tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4866 AMX-INT8 :{VEX} TDPBSUD tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4867 AMX-INT8 :{VEX} TDPBUSD tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4868 AMX-INT8 :{VEX} TDPBUUD tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4869 AMX-TILE :{VEX} TILEZERO tmm (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4870 AMX-TILE :{VEX} TILERELEASE L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4871 AMX-TILE :{VEX} LDTILECFG [m512] L: [memory dep.] T: 0.00ns= 0.000c 4872 AMX-TILE :{VEX} STTILECFG [m512] L: [memory dep.] T: 0.00ns= 0.000c 4873 AMX-TILE :{VEX} TILELOADD tmm, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 4874 AMX-TILE :{VEX} TILELOADDT1 tmm, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 4875 AMX-TILE :{VEX} TILESTORED [sibmem], tmm (64x16) L: [memory dep.] T: 0.00ns= 0.000c 4876 AMX-TILE :{VEX} TILE L+S [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 4877 AMX-FP16 :{VEX} TDPFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4878 AMX-COMPLEX :{VEX} TCMMIMFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4879 AMX-COMPLEX :{VEX} TCMMRLFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4880 AVX_IFMA :{VEX} VPMADD52LUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4881 AVX_IFMA :{VEX} VPMADD52LUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4882 AVX_IFMA :{VEX} VPMADD52HUQ xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4883 AVX_IFMA :{VEX} VPMADD52HUQ ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4884 AVX_VNNI_INT8 :{VEX} VPDPBSSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4885 AVX_VNNI_INT8 :{VEX} VPDPBSSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4886 AVX_VNNI_INT8 :{VEX} VPDPBSSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4887 AVX_VNNI_INT8 :{VEX} VPDPBSSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4888 AVX_VNNI_INT8 :{VEX} VPDPBSUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4889 AVX_VNNI_INT8 :{VEX} VPDPBSUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4890 AVX_VNNI_INT8 :{VEX} VPDPBSUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4891 AVX_VNNI_INT8 :{VEX} VPDPBSUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4892 AVX_VNNI_INT8 :{VEX} VPDPBUUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4893 AVX_VNNI_INT8 :{VEX} VPDPBUUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4894 AVX_VNNI_INT8 :{VEX} VPDPBUUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4895 AVX_VNNI_INT8 :{VEX} VPDPBUUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4896 AVX_NE_CONVERT :{VEX} VBCSTNEBF162PS xmm1, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4897 AVX_NE_CONVERT :{VEX} VBCSTNEBF162PS ymm1, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4898 AVX_NE_CONVERT :{VEX} VBCSTNESH2PS xmm1, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4899 AVX_NE_CONVERT :{VEX} VBCSTNESH2PS ymm1, [m16] L: [memory dep.] T: 0.00ns= 0.000c 4900 AVX_NE_CONVERT :{VEX} VCVTNEEBF162PS xmm1, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4901 AVX_NE_CONVERT :{VEX} VCVTNEEBF162PS ymm1, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4902 AVX_NE_CONVERT :{VEX} VCVTNEEPH2PS xmm1, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4903 AVX_NE_CONVERT :{VEX} VCVTNEEPH2PS ymm1, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4904 AVX_NE_CONVERT :{VEX} VCVTNEOBF162PS xmm1, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4905 AVX_NE_CONVERT :{VEX} VCVTNEOBF162PS ymm1, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4906 AVX_NE_CONVERT :{VEX} VCVTNEOPH2PS xmm1, [m128] L: [memory dep.] T: 0.00ns= 0.000c 4907 AVX_NE_CONVERT :{VEX} VCVTNEOPH2PS ymm1, [m256] L: [memory dep.] T: 0.00ns= 0.000c 4908 AVX_NE_CONVERT :{VEX} VCVTNEPS2BF16 xmm1, xmm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4909 AVX_NE_CONVERT :{VEX} VCVTNEPS2BF16 xmm1, ymm2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4910 CMPCCXADD :{VEX} CMPBEXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4911 CMPCCXADD :{VEX} CMPBEXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4912 CMPCCXADD :{VEX} CMPBXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4913 CMPCCXADD :{VEX} CMPBXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4914 CMPCCXADD :{VEX} CMPLEXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4915 CMPCCXADD :{VEX} CMPLEXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4916 CMPCCXADD :{VEX} CMPLXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4917 CMPCCXADD :{VEX} CMPLXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4918 CMPCCXADD :{VEX} CMPNBEXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4919 CMPCCXADD :{VEX} CMPNBEXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4920 CMPCCXADD :{VEX} CMPNBXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4921 CMPCCXADD :{VEX} CMPNBXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4922 CMPCCXADD :{VEX} CMPNLEXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4923 CMPCCXADD :{VEX} CMPNLEXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4924 CMPCCXADD :{VEX} CMPNLXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4925 CMPCCXADD :{VEX} CMPNLXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4926 CMPCCXADD :{VEX} CMPNOXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4927 CMPCCXADD :{VEX} CMPNOXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4928 CMPCCXADD :{VEX} CMPNPXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4929 CMPCCXADD :{VEX} CMPNPXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4930 CMPCCXADD :{VEX} CMPNSXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4931 CMPCCXADD :{VEX} CMPNSXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4932 CMPCCXADD :{VEX} CMPNZXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4933 CMPCCXADD :{VEX} CMPNZXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4934 CMPCCXADD :{VEX} CMPOXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4935 CMPCCXADD :{VEX} CMPOXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4936 CMPCCXADD :{VEX} CMPPXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4937 CMPCCXADD :{VEX} CMPPXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4938 CMPCCXADD :{VEX} CMPSXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4939 CMPCCXADD :{VEX} CMPSXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4940 CMPCCXADD :{VEX} CMPZXADD [m32], r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4941 CMPCCXADD :{VEX} CMPZXADD [m64], r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4942 PREFETCHI :{REX} PREFETCHIT0 [rip+disp32] L: [memory dep.] T: 0.00ns= 0.000c 4943 PREFETCHI :{REX} PREFETCHIT1 [rip+disp32] L: [memory dep.] T: 0.00ns= 0.000c 4944 RAO_INT :{REX} AADD [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 4945 RAO_INT :{REX} AADD [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 4946 RAO_INT :{REX} AAND [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 4947 RAO_INT :{REX} AAND [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 4948 RAO_INT :{REX} AOR [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 4949 RAO_INT :{REX} AOR [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 4950 RAO_INT :{REX} AXOR [m32], r32 L: [memory dep.] T: 0.00ns= 0.000c 4951 RAO_INT :{REX} AXOR [m64], r64 L: [memory dep.] T: 0.00ns= 0.000c 4952 AVX512VLBW :{EVEX} VPADDB xmm{k}{z}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4953 AVX512VLBW :{EVEX} VPADDB ymm{k}{z}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4954 AVX512BW :{EVEX} VPADDB zmm{k}{z}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4955 AVX512VLBW :{EVEX} VPADDW xmm{k}{z}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4956 AVX512VLBW :{EVEX} VPADDW ymm{k}{z}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4957 AVX512BW :{EVEX} VPADDW zmm{k}{z}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4958 AVX512VL :{EVEX} VPADDD xmm{k}{z}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4959 AVX512VL :{EVEX} VPADDD ymm{k}{z}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4960 AVX512F :{EVEX} VPADDD zmm{k}{z}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4961 AVX512VL :{EVEX} VPADDQ xmm{k}{z}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4962 AVX512VL :{EVEX} VPADDQ ymm{k}{z}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4963 AVX512F :{EVEX} VPADDQ zmm{k}{z}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4964 AVX512VLBW :{EVEX} VDBPSADBW xmm{k}{z}, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4965 AVX512VLBW :{EVEX} VDBPSADBW ymm{k}{z}, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4966 AVX512BW :{EVEX} VDBPSADBW zmm{k}{z}, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4967 AVX512VLBW :{EVEX} VPMADDUBSW xmm{k}{z}, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4968 AVX512VLBW :{EVEX} VPMADDUBSW ymm{k}{z}, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4969 AVX512BW :{EVEX} VPMADDUBSW zmm{k}{z}, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4970 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB x{k}{z},x,x,i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4971 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB y{k}{z},y,y,i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4972 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB z{k}{z}, z, z, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4973 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB+VPADDB x{k}{z} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4974 AVX512VL+GFNI :{EVEX} VGF2P8AFFINEQB+VPADDB y{k}{z} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4975 AVX512F+GFNI :{EVEX} VGF2P8AFFINEQB+VPADDB z{k}{z} L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4976 AVX512DQ :{VEX} KANDNB k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4977 AVX512F :{VEX} KANDNW k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4978 AVX512BW :{VEX} KANDND k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4979 AVX512BW :{VEX} KANDNQ k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4980 AVX512DQ :{VEX} KXNORB k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4981 AVX512F :{VEX} KXNORW k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4982 AVX512BW :{VEX} KXNORD k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4983 AVX512BW :{VEX} KXNORQ k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4984 AVX512DQ :{VEX} KXORB k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4985 AVX512F :{VEX} KXORW k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4986 AVX512BW :{VEX} KXORD k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4987 AVX512BW :{VEX} KXORQ k1, k1, k2 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4988 AVX_VNNI_INT16 :{VEX} VPDPWUSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4989 AVX_VNNI_INT16 :{VEX} VPDPWUSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4990 AVX_VNNI_INT16 :{VEX} VPDPWUSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4991 AVX_VNNI_INT16 :{VEX} VPDPWUSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4992 AVX_VNNI_INT16 :{VEX} VPDPWSUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4993 AVX_VNNI_INT16 :{VEX} VPDPWSUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4994 AVX_VNNI_INT16 :{VEX} VPDPWSUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4995 AVX_VNNI_INT16 :{VEX} VPDPWSUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4996 AVX_VNNI_INT16 :{VEX} VPDPWUUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4997 AVX_VNNI_INT16 :{VEX} VPDPWUUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4998 AVX_VNNI_INT16 :{VEX} VPDPWUUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 4999 AVX_VNNI_INT16 :{VEX} VPDPWUUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5000 SHA512 :{VEX} VSHA512RNDS2 ymm, ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5001 SHA512 :{VEX} VSHA512MSG1 ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5002 SHA512 :{VEX} VSHA512MSG2 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5003 SM3 :{VEX} VSM3RNDS2 xmm, xmm, xmm, i8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5004 SM3 :{VEX} VSM3MSG1 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5005 SM3 :{VEX} VSM3MSG2 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5006 SM4 :{VEX} VSM4RNDS4 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5007 SM4 :{VEX} VSM4RNDS4 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5008 SM4 :{VEX} VSM4KEY4 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5009 SM4 :{VEX} VSM4KEY4 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5010 AVX512_FP16 :{EVEX} VFMADD231SH+VADDSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5011 AVX512VL_FP16 :{EVEX} VFMADD231PH+VADDPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5012 AVX512VL_FP16 :{EVEX} VFMADD231PH+VADDPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5013 AVX512_FP16 :{EVEX} VFMADD231PH+VADDPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5014 AVX512_FP16 :{EVEX} VFMADD231SH+VMULSH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5015 AVX512VL_FP16 :{EVEX} VFMADD231PH+VMULPH xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5016 AVX512VL_FP16 :{EVEX} VFMADD231PH+VMULPH ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5017 AVX512_FP16 :{EVEX} VFMADD231PH+VMULPH zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5018 FMA3 :{VEX} VFMADD231SS+VADDSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5019 FMA3 :{VEX} VFMADD231PS+VADDPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5020 FMA3 :{VEX} VFMADD231PS+VADDPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5021 AVX512F :{EVEX} VFMADD231PS+VADDPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5022 FMA3 :{VEX} VFMADD231SS+VMULSS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5023 FMA3 :{VEX} VFMADD231PS+VMULPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5024 FMA3 :{VEX} VFMADD231PS+VMULPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5025 AVX512F :{EVEX} VFMADD231PS+VMULPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5026 FMA3 :{VEX} VFMADD231SD+VADDSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5027 FMA3 :{VEX} VFMADD231PD+VADDPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5028 FMA3 :{VEX} VFMADD231PD+VADDPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5029 AVX512F :{EVEX} VFMADD231PD+VADDPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5030 FMA3 :{VEX} VFMADD231SD+VMULSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5031 FMA3 :{VEX} VFMADD231PD+VMULPD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5032 FMA3 :{VEX} VFMADD231PD+VMULPD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5033 AVX512F :{EVEX} VFMADD231PD+VMULPD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5034 AESKLE :{REX} AESENC128KL xmm, [m384] L: [memory dep.] T: 0.00ns= 0.000c 5035 AESKLE :{REX} AESDEC128KL xmm, [m384] L: [memory dep.] T: 0.00ns= 0.000c 5036 AESKLE :{REX} AESENC256KL xmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5037 AESKLE :{REX} AESDEC256KL xmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5038 WIDE_KL :{REX} AESENCWIDE128KL [m384] L: [memory dep.] T: 0.00ns= 0.000c 5039 WIDE_KL :{REX} AESDECWIDE128KL [m384] L: [memory dep.] T: 0.00ns= 0.000c 5040 WIDE_KL :{REX} AESENCWIDE256KL [m512] L: [memory dep.] T: 0.00ns= 0.000c 5041 WIDE_KL :{REX} AESDECWIDE256KL [m512] L: [memory dep.] T: 0.00ns= 0.000c 5042 AESKLE :{REX} ENCODEKEY128 r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5043 AESKLE :{REX} ENCODEKEY256 r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5044 KEYLOCK :{REX} LOADIWKEY xmm, xmm L: [memory dep.] T: 0.00ns= 0.000c 5045 AVX10+SM4 :{EVEX} VSM4KEY4 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5046 AVX10+SM4 :{EVEX} VSM4KEY4 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5047 AVX10+SM4 :{EVEX} VSM4KEY4 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5048 AVX10+SM4 :{EVEX} VSM4RNDS4 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5049 AVX10+SM4 :{EVEX} VSM4RNDS4 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5050 AVX10+SM4 :{EVEX} VSM4RNDS4 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5051 AVX10_VNNI_INT :{EVEX} VPDPBSSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5052 AVX10_VNNI_INT :{EVEX} VPDPBSSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5053 AVX10_VNNI_INT :{EVEX} VPDPBSSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5054 AVX10_VNNI_INT :{EVEX} VPDPBSSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5055 AVX10_VNNI_INT :{EVEX} VPDPBSSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5056 AVX10_VNNI_INT :{EVEX} VPDPBSSDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5057 AVX10_VNNI_INT :{EVEX} VPDPBSUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5058 AVX10_VNNI_INT :{EVEX} VPDPBSUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5059 AVX10_VNNI_INT :{EVEX} VPDPBSUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5060 AVX10_VNNI_INT :{EVEX} VPDPBSUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5061 AVX10_VNNI_INT :{EVEX} VPDPBSUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5062 AVX10_VNNI_INT :{EVEX} VPDPBSUDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5063 AVX10_VNNI_INT :{EVEX} VPDPBUUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5064 AVX10_VNNI_INT :{EVEX} VPDPBUUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5065 AVX10_VNNI_INT :{EVEX} VPDPBUUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5066 AVX10_VNNI_INT :{EVEX} VPDPBUUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5067 AVX10_VNNI_INT :{EVEX} VPDPBUUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5068 AVX10_VNNI_INT :{EVEX} VPDPBUUDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5069 AVX10_VNNI_INT :{EVEX} VPDPWSUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5070 AVX10_VNNI_INT :{EVEX} VPDPWSUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5071 AVX10_VNNI_INT :{EVEX} VPDPWSUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5072 AVX10_VNNI_INT :{EVEX} VPDPWSUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5073 AVX10_VNNI_INT :{EVEX} VPDPWSUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5074 AVX10_VNNI_INT :{EVEX} VPDPWSUDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5075 AVX10_VNNI_INT :{EVEX} VPDPWUSD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5076 AVX10_VNNI_INT :{EVEX} VPDPWUSD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5077 AVX10_VNNI_INT :{EVEX} VPDPWUSD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5078 AVX10_VNNI_INT :{EVEX} VPDPWUSDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5079 AVX10_VNNI_INT :{EVEX} VPDPWUSDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5080 AVX10_VNNI_INT :{EVEX} VPDPWUSDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5081 AVX10_VNNI_INT :{EVEX} VPDPWUUD xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5082 AVX10_VNNI_INT :{EVEX} VPDPWUUD ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5083 AVX10_VNNI_INT :{EVEX} VPDPWUUD zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5084 AVX10_VNNI_INT :{EVEX} VPDPWUUDS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5085 AVX10_VNNI_INT :{EVEX} VPDPWUUDS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5086 AVX10_VNNI_INT :{EVEX} VPDPWUUDS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5087 AVX10.2 :{EVEX} VDPPHPS xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5088 AVX10.2 :{EVEX} VDPPHPS ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5089 AVX10.2 :{EVEX} VDPPHPS zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5090 AVX10.2 :{EVEX} VMPSADBW xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5091 AVX10.2 :{EVEX} VMPSADBW ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5092 AVX10.2 :{EVEX} VMPSADBW zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5093 AVX10.2 :{EVEX} VMINMAXBF16 xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5094 AVX10.2 :{EVEX} VMINMAXBF16 ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5095 AVX10.2 :{EVEX} VMINMAXBF16 zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5096 AVX10.2 :{EVEX} VMINMAXPD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5097 AVX10.2 :{EVEX} VMINMAXPD ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5098 AVX10.2 :{EVEX} VMINMAXPD zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5099 AVX10.2 :{EVEX} VMINMAXPH xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5100 AVX10.2 :{EVEX} VMINMAXPH ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5101 AVX10.2 :{EVEX} VMINMAXPH zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5102 AVX10.2 :{EVEX} VMINMAXPS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5103 AVX10.2 :{EVEX} VMINMAXPS ymm, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5104 AVX10.2 :{EVEX} VMINMAXPS zmm, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5105 AVX10.2 :{EVEX} VMINMAXSD xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5106 AVX10.2 :{EVEX} VMINMAXSH xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5107 AVX10.2 :{EVEX} VMINMAXSS xmm, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5108 AVX10.2 :{EVEX} VADDBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5109 AVX10.2 :{EVEX} VADDBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5110 AVX10.2 :{EVEX} VADDBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5111 AVX10.2 :{EVEX} VSUBBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5112 AVX10.2 :{EVEX} VSUBBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5113 AVX10.2 :{EVEX} VSUBBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5114 AVX10.2 :{EVEX} VMULBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5115 AVX10.2 :{EVEX} VMULBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5116 AVX10.2 :{EVEX} VMULBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5117 AVX10.2 :{EVEX} VMINBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5118 AVX10.2 :{EVEX} VMINBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5119 AVX10.2 :{EVEX} VMINBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5120 AVX10.2 :{EVEX} VMAXBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5121 AVX10.2 :{EVEX} VMAXBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5122 AVX10.2 :{EVEX} VMAXBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5123 AVX10.2 :{EVEX} VCMPBF16 k1, xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5124 AVX10.2 :{EVEX} VCMPBF16 k1, ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5125 AVX10.2 :{EVEX} VCMPBF16 k1, zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5126 AVX10.2 :{EVEX} VCOMISBF16 xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5127 AVX10.2 :{EVEX} VCOMXSD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5128 AVX10.2 :{EVEX} VCOMISH xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5129 AVX10.2 :{EVEX} VCOMXSS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5130 AVX10.2 :{EVEX} VUCOMXSD xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5131 AVX10.2 :{EVEX} VUCOMISH xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5132 AVX10.2 :{EVEX} VUCOMXSS xmm, xmm L: [no true dep.] T: 0.00ns= 0.000c 5133 AVX10.2 :{EVEX} VDIVBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5134 AVX10.2 :{EVEX} VDIVBF16 xmm (0.0bf16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5135 AVX10.2 :{EVEX} VDIVBF16 xmm (x/1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5136 AVX10.2 :{EVEX} VDIVBF16 xmm (x/2.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5137 AVX10.2 :{EVEX} VDIVBF16 xmm (x/0.5bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5138 AVX10.2 :{EVEX} VDIVBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5139 AVX10.2 :{EVEX} VDIVBF16 ymm (0.0bf16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5140 AVX10.2 :{EVEX} VDIVBF16 ymm (x/1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5141 AVX10.2 :{EVEX} VDIVBF16 ymm (x/2.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5142 AVX10.2 :{EVEX} VDIVBF16 ymm (x/0.5bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5143 AVX10.2 :{EVEX} VDIVBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5144 AVX10.2 :{EVEX} VDIVBF16 zmm (0.0bf16/x) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5145 AVX10.2 :{EVEX} VDIVBF16 zmm (x/1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5146 AVX10.2 :{EVEX} VDIVBF16 zmm (x/2.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5147 AVX10.2 :{EVEX} VDIVBF16 zmm (x/0.5bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5148 AVX10.2 :{EVEX} VSQRTBF16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5149 AVX10.2 :{EVEX} VSQRTBF16 xmm (0.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5150 AVX10.2 :{EVEX} VSQRTBF16 xmm (1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5151 AVX10.2 :{EVEX} VSQRTBF16 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5152 AVX10.2 :{EVEX} VSQRTBF16 ymm (0.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5153 AVX10.2 :{EVEX} VSQRTBF16 ymm (1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5154 AVX10.2 :{EVEX} VSQRTBF16 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5155 AVX10.2 :{EVEX} VSQRTBF16 zmm (0.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5156 AVX10.2 :{EVEX} VSQRTBF16 zmm (1.0bf16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5157 AVX10.2 :{EVEX} VRCPBF16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5158 AVX10.2 :{EVEX} VRCPBF16 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5159 AVX10.2 :{EVEX} VRCPBF16 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5160 AVX10.2 :{EVEX} VRSQRTBF16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5161 AVX10.2 :{EVEX} VRSQRTBF16 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5162 AVX10.2 :{EVEX} VRSQRTBF16 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5163 AVX10.2 :{EVEX} VFMADD132BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5164 AVX10.2 :{EVEX} VFMADD132BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5165 AVX10.2 :{EVEX} VFMADD132BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5166 AVX10.2 :{EVEX} VFMADD213BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5167 AVX10.2 :{EVEX} VFMADD213BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5168 AVX10.2 :{EVEX} VFMADD213BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5169 AVX10.2 :{EVEX} VFMADD231BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5170 AVX10.2 :{EVEX} VFMADD231BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5171 AVX10.2 :{EVEX} VFMADD231BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5172 AVX10.2 :{EVEX} VFMSUB132BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5173 AVX10.2 :{EVEX} VFMSUB132BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5174 AVX10.2 :{EVEX} VFMSUB132BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5175 AVX10.2 :{EVEX} VFMSUB213BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5176 AVX10.2 :{EVEX} VFMSUB213BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5177 AVX10.2 :{EVEX} VFMSUB213BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5178 AVX10.2 :{EVEX} VFMSUB231BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5179 AVX10.2 :{EVEX} VFMSUB231BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5180 AVX10.2 :{EVEX} VFMSUB231BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5181 AVX10.2 :{EVEX} VFNMADD132BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5182 AVX10.2 :{EVEX} VFNMADD132BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5183 AVX10.2 :{EVEX} VFNMADD132BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5184 AVX10.2 :{EVEX} VFNMADD213BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5185 AVX10.2 :{EVEX} VFNMADD213BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5186 AVX10.2 :{EVEX} VFNMADD213BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5187 AVX10.2 :{EVEX} VFNMADD231BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5188 AVX10.2 :{EVEX} VFNMADD231BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5189 AVX10.2 :{EVEX} VFNMADD231BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5190 AVX10.2 :{EVEX} VFNMSUB132BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5191 AVX10.2 :{EVEX} VFNMSUB132BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5192 AVX10.2 :{EVEX} VFNMSUB132BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5193 AVX10.2 :{EVEX} VFNMSUB213BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5194 AVX10.2 :{EVEX} VFNMSUB213BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5195 AVX10.2 :{EVEX} VFNMSUB213BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5196 AVX10.2 :{EVEX} VFNMSUB231BF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5197 AVX10.2 :{EVEX} VFNMSUB231BF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5198 AVX10.2 :{EVEX} VFNMSUB231BF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5199 AVX10.2 :{EVEX} VFPCLASSBF16 k, xmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 5200 AVX10.2 :{EVEX} VFPCLASSBF16 k, ymm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 5201 AVX10.2 :{EVEX} VFPCLASSBF16 k, zmm, imm8 L: [diff. reg. set] T: 0.00ns= 0.000c 5202 AVX10.2 :{EVEX} VGETEXPBF16 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5203 AVX10.2 :{EVEX} VGETEXPBF16 ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5204 AVX10.2 :{EVEX} VGETEXPBF16 zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5205 AVX10.2 :{EVEX} VGETMANTBF16 xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5206 AVX10.2 :{EVEX} VGETMANTBF16 ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5207 AVX10.2 :{EVEX} VGETMANTBF16 zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5208 AVX10.2 :{EVEX} VREDUCEBF16 xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5209 AVX10.2 :{EVEX} VREDUCEBF16 ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5210 AVX10.2 :{EVEX} VREDUCEBF16 zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5211 AVX10.2 :{EVEX} VRNDSCALEBF16 xmm, xmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5212 AVX10.2 :{EVEX} VRNDSCALEBF16 ymm, ymm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5213 AVX10.2 :{EVEX} VRNDSCALEBF16 zmm, zmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5214 AVX10.2 :{EVEX} VSCALEFBF16 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5215 AVX10.2 :{EVEX} VSCALEFBF16 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5216 AVX10.2 :{EVEX} VSCALEFBF16 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5217 AVX10.2 :{EVEX} VMOVW xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5218 AVX10.2 :{EVEX} VMOVD xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5219 AVX512F_X64 :{EVEX} VMOVQ xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5220 AVX10.2 :{EVEX} VCVT2PH2BF8 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5221 AVX10.2 :{EVEX} VCVT2PH2BF8 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5222 AVX10.2 :{EVEX} VCVT2PH2BF8 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5223 AVX10.2 :{EVEX} VCVT2PH2BF8S xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5224 AVX10.2 :{EVEX} VCVT2PH2BF8S ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5225 AVX10.2 :{EVEX} VCVT2PH2BF8S zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5226 AVX10.2 :{EVEX} VCVT2PH2HF8 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5227 AVX10.2 :{EVEX} VCVT2PH2HF8 ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5228 AVX10.2 :{EVEX} VCVT2PH2HF8 zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5229 AVX10.2 :{EVEX} VCVT2PH2HF8S xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5230 AVX10.2 :{EVEX} VCVT2PH2HF8S ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5231 AVX10.2 :{EVEX} VCVT2PH2HF8S zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5232 AVX10.2 :{EVEX} VCVTPH2BF8 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5233 AVX10.2 :{EVEX} VCVTPH2BF8 xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5234 AVX10.2 :{EVEX} VCVTPH2BF8 ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5235 AVX10.2 :{EVEX} VCVTPH2BF8S xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5236 AVX10.2 :{EVEX} VCVTPH2BF8S xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5237 AVX10.2 :{EVEX} VCVTPH2BF8S ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5238 AVX10.2 :{EVEX} VCVTPH2HF8 xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5239 AVX10.2 :{EVEX} VCVTPH2HF8 xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5240 AVX10.2 :{EVEX} VCVTPH2HF8 ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5241 AVX10.2 :{EVEX} VCVTPH2HF8S xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5242 AVX10.2 :{EVEX} VCVTPH2HF8S xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5243 AVX10.2 :{EVEX} VCVTPH2HF8S ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5244 AVX10.2 :{EVEX} VCVT2PS2PHX xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5245 AVX10.2 :{EVEX} VCVT2PS2PHX ymm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5246 AVX10.2 :{EVEX} VCVT2PS2PHX zmm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5247 AVX10.2 :{EVEX} VCVTBIASPH2BF8 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5248 AVX10.2 :{EVEX} VCVTBIASPH2BF8 xmm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5249 AVX10.2 :{EVEX} VCVTBIASPH2BF8 ymm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5250 AVX10.2 :{EVEX} VCVTBIASPH2BF8S xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5251 AVX10.2 :{EVEX} VCVTBIASPH2BF8S xmm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5252 AVX10.2 :{EVEX} VCVTBIASPH2BF8S ymm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5253 AVX10.2 :{EVEX} VCVTBIASPH2HF8 xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5254 AVX10.2 :{EVEX} VCVTBIASPH2HF8 xmm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5255 AVX10.2 :{EVEX} VCVTBIASPH2HF8 ymm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5256 AVX10.2 :{EVEX} VCVTBIASPH2HF8S xmm, xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5257 AVX10.2 :{EVEX} VCVTBIASPH2HF8S xmm, ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5258 AVX10.2 :{EVEX} VCVTBIASPH2HF8S ymm, zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5259 AVX10.2 :{EVEX} VCVTHF82PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5260 AVX10.2 :{EVEX} VCVTHF82PH xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5261 AVX10.2 :{EVEX} VCVTHF82PH ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5262 AVX10.2 :{EVEX} VCVTBF162IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5263 AVX10.2 :{EVEX} VCVTBF162IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5264 AVX10.2 :{EVEX} VCVTBF162IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5265 AVX10.2 :{EVEX} VCVTBF162IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5266 AVX10.2 :{EVEX} VCVTBF162IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5267 AVX10.2 :{EVEX} VCVTBF162IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5268 AVX10.2 :{EVEX} VCVTTBF162IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5269 AVX10.2 :{EVEX} VCVTTBF162IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5270 AVX10.2 :{EVEX} VCVTTBF162IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5271 AVX10.2 :{EVEX} VCVTTBF162IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5272 AVX10.2 :{EVEX} VCVTTBF162IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5273 AVX10.2 :{EVEX} VCVTTBF162IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5274 AVX10.2 :{EVEX} VCVTTPD2DQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5275 AVX10.2 :{EVEX} VCVTTPD2DQS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5276 AVX10.2 :{EVEX} VCVTTPD2DQS ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5277 AVX10.2 :{EVEX} VCVTTPD2QQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5278 AVX10.2 :{EVEX} VCVTTPD2QQS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5279 AVX10.2 :{EVEX} VCVTTPD2QQS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5280 AVX10.2 :{EVEX} VCVTTPD2UDQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5281 AVX10.2 :{EVEX} VCVTTPD2UDQS xmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5282 AVX10.2 :{EVEX} VCVTTPD2UDQS ymm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5283 AVX10.2 :{EVEX} VCVTTPD2UQQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5284 AVX10.2 :{EVEX} VCVTTPD2UQQS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5285 AVX10.2 :{EVEX} VCVTTPD2UQQS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5286 AVX10.2 :{EVEX} VCVTPH2IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5287 AVX10.2 :{EVEX} VCVTPH2IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5288 AVX10.2 :{EVEX} VCVTPH2IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5289 AVX10.2 :{EVEX} VCVTPH2IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5290 AVX10.2 :{EVEX} VCVTPH2IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5291 AVX10.2 :{EVEX} VCVTPH2IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5292 AVX10.2 :{EVEX} VCVTTPH2IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5293 AVX10.2 :{EVEX} VCVTTPH2IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5294 AVX10.2 :{EVEX} VCVTTPH2IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5295 AVX10.2 :{EVEX} VCVTTPH2IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5296 AVX10.2 :{EVEX} VCVTTPH2IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5297 AVX10.2 :{EVEX} VCVTTPH2IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5298 AVX10.2 :{EVEX} VCVTTPS2DQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5299 AVX10.2 :{EVEX} VCVTTPS2DQS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5300 AVX10.2 :{EVEX} VCVTTPS2DQS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5301 AVX10.2 :{EVEX} VCVTTPS2QQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5302 AVX10.2 :{EVEX} VCVTTPS2QQS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5303 AVX10.2 :{EVEX} VCVTTPS2QQS zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5304 AVX10.2 :{EVEX} VCVTTPS2UDQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5305 AVX10.2 :{EVEX} VCVTTPS2UDQS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5306 AVX10.2 :{EVEX} VCVTTPS2UDQS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5307 AVX10.2 :{EVEX} VCVTTPS2UQQS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5308 AVX10.2 :{EVEX} VCVTTPS2UQQS ymm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5309 AVX10.2 :{EVEX} VCVTTPS2UQQS zmm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5310 AVX10.2 :{EVEX} VCVTPS2IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5311 AVX10.2 :{EVEX} VCVTPS2IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5312 AVX10.2 :{EVEX} VCVTPS2IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5313 AVX10.2 :{EVEX} VCVTPS2IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5314 AVX10.2 :{EVEX} VCVTPS2IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5315 AVX10.2 :{EVEX} VCVTPS2IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5316 AVX10.2 :{EVEX} VCVTTPS2IBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5317 AVX10.2 :{EVEX} VCVTTPS2IBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5318 AVX10.2 :{EVEX} VCVTTPS2IBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5319 AVX10.2 :{EVEX} VCVTTPS2IUBS xmm, xmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5320 AVX10.2 :{EVEX} VCVTTPS2IUBS ymm, ymm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5321 AVX10.2 :{EVEX} VCVTTPS2IUBS zmm, zmm L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5322 AVX10.2 :{EVEX} VCVTTSD2SIS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5323 AVX10.2_X64 :{EVEX} VCVTTSD2SIS r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5324 AVX10.2 :{EVEX} VCVTTSD2USIS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5325 AVX10.2_X64 :{EVEX} VCVTTSD2USIS r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5326 AVX10.2 :{EVEX} VCVTTSS2SIS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5327 AVX10.2_X64 :{EVEX} VCVTTSS2SIS r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5328 AVX10.2 :{EVEX} VCVTTSS2USIS r32, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5329 AVX10.2_X64 :{EVEX} VCVTTSS2USIS r64, xmm L: [diff. reg. set] T: 0.00ns= 0.000c 5330 AVX10.2 :{EVEX} VCVTTSD2SIS + VCVTSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5331 AVX10.2_X64 :{EVEX} VCVTTSD2SIS + VCVTSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5332 AVX10.2 :{EVEX} VCVTTSD2USIS + VCVTUSI2SD r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5333 AVX10.2_X64 :{EVEX} VCVTTSD2USIS + VCVTUSI2SD r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5334 AVX10.2 :{EVEX} VCVTTSS2SI + VCVTSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5335 AVX10.2_X64 :{EVEX} VCVTTSS2SI + VCVTSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5336 AVX10.2 :{EVEX} VCVTTSS2USI + VCVTUSI2SS r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5337 AVX10.2_X64 :{EVEX} VCVTTSS2USI + VCVTUSI2SS r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5338 MOVRS :{REX} MOVRS r8, [m8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5339 MOVRS :{REX} MOVRS r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5340 MOVRS :{REX} MOVRS r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5341 MOVRS :{REX} MOVRS r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5342 MOVRS :{REX} PREFETCHRST2 [mem] L: [memory dep.] T: 0.00ns= 0.000c 5343 AVX10+MOVRS :{EVEX} VMOVRSB xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 5344 AVX10+MOVRS :{EVEX} VMOVRSB ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 5345 AVX10+MOVRS :{EVEX} VMOVRSB zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5346 AVX10+MOVRS :{EVEX} VMOVRSW xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 5347 AVX10+MOVRS :{EVEX} VMOVRSW ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 5348 AVX10+MOVRS :{EVEX} VMOVRSW zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5349 AVX10+MOVRS :{EVEX} VMOVRSD xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 5350 AVX10+MOVRS :{EVEX} VMOVRSD ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 5351 AVX10+MOVRS :{EVEX} VMOVRSD zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5352 AVX10+MOVRS :{EVEX} VMOVRSQ xmm, [m128] L: [memory dep.] T: 0.00ns= 0.000c 5353 AVX10+MOVRS :{EVEX} VMOVRSQ ymm, [m256] L: [memory dep.] T: 0.00ns= 0.000c 5354 AVX10+MOVRS :{EVEX} VMOVRSQ zmm, [m512] L: [memory dep.] T: 0.00ns= 0.000c 5355 AMX-TRANSPOSE :{VEX} T2RPNTLVWZ0 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5356 AMX-TRANSPOSE :{VEX} T2RPNTLVWZ0T1 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5357 AMX-TRANSPOSE :{VEX} T2RPNTLVWZ1 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5358 AMX-TRANSPOSE :{VEX} T2RPNTLVWZ1T1 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5359 AMX-TRANSPOSE+MOVRS :{VEX} T2RPNTLVWZ0RS tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5360 AMX-TRANSPOSE+MOVRS :{VEX} T2RPNTLVWZ0RST1 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5361 AMX-TRANSPOSE+MOVRS :{VEX} T2RPNTLVWZ1RS tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5362 AMX-TRANSPOSE+MOVRS :{VEX} T2RPNTLVWZ1RST1 tmm+1, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5363 AMX-TRANSPOSE :{VEX} TTRANSPOSED tmm, tmm (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5364 AMX-TRANSPOSE+CMPLX :{VEX} TCONJTCMMIMFP16PS tm1, tm2, tm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5365 AMX-TRANSPOSE+CMPLX :{VEX} TCONJTFP16 tmm, tmm (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5366 AMX-TRANSPOSE+CMPLX :{VEX} TTCMMIMFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5367 AMX-TRANSPOSE+CMPLX :{VEX} TTCMMRLFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5368 AVX10+AMX_AVX512 :{EVEX} TCVTROWD2PS zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5369 AVX10+AMX_AVX512 :{EVEX} TCVTROWD2PS zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5370 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2BF16H zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5371 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2BF16H zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5372 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2BF16L zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5373 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2BF16L zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5374 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2PHH zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5375 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2PHH zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5376 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2PHL zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5377 AVX10+AMX_AVX512 :{EVEX} TCVTROWPS2PHL zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5378 AVX10+AMX_AVX512 :{EVEX} TILEMOVROW zmm, tmm, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5379 AVX10+AMX_AVX512 :{EVEX} TILEMOVROW zmm, tmm, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5380 AMX-FP8 :{VEX} TDPBF8PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5381 AMX-FP8 :{VEX} TDPBHF8PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5382 AMX-FP8 :{VEX} TDPHBF8PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5383 AMX-FP8 :{VEX} TDPHF8PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5384 AMX-MOVRS :{VEX} TILELOADDRS tmm, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5385 AMX-MOVRS :{VEX} TILELOADDRST1 tmm, [sibmem] (64x16) L: [memory dep.] T: 0.00ns= 0.000c 5386 AMX-TF32 :{VEX} TMMULTF32PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5387 AMX-TRANSPOSE+BF16 :{VEX} TTDPBF16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5388 AMX-TRANSPOSE+FP16 :{VEX} TTDPFP16PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5389 AMX-TRANSPOSE+TF32 :{VEX} TTMMULTF32PS tmm1, tmm2, tmm3 (64x16) L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5390 AVX :{VEX} VEXTRACTF128 xmm, ymm, 00h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5391 AVX :{VEX} VEXTRACTF128 xmm, ymm, 01h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5392 AVX :{VEX} VINSERTF128 ym, ym, xm, 00h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5393 AVX :{VEX} VINSERTF128 ym, ym, xm, 01h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5394 AVX :{VEX} VPERM2F128 ym, ym, ym, 00h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5395 AVX :{VEX} VPERM2F128 ym, ym, ym, 10h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5396 AVX :{VEX} VPERM2F128 ym, ym, ym, 12h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5397 AVX :{VEX} VPERM2F128 ym, ym, ym, 30h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5398 AVX :{VEX} VPERM2F128 ym, ym, ym, 32h L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5399 AVX :{VEX} VPEXTRD r32, xmm, 0 L: [diff. reg. set] T: 0.00ns= 0.000c 5400 AVX :{VEX} VPEXTRD r32, xmm, 1 L: [diff. reg. set] T: 0.00ns= 0.000c 5401 AVX :{VEX} VPEXTRD r32, xmm, 2 L: [diff. reg. set] T: 0.00ns= 0.000c 5402 AVX :{VEX} VPEXTRD r32, xmm, 3 L: [diff. reg. set] T: 0.00ns= 0.000c 5403 AVX :{VEX} VPINSRD xmm1, xmm2, r32, 0 L: [diff. reg. set] T: 0.00ns= 0.000c 5404 AVX :{VEX} VPINSRD xmm1, xmm2, r32, 1 L: [diff. reg. set] T: 0.00ns= 0.000c 5405 AVX :{VEX} VPINSRD xmm1, xmm2, r32, 2 L: [diff. reg. set] T: 0.00ns= 0.000c 5406 AVX :{VEX} VPINSRD xmm1, xmm2, r32, 3 L: [diff. reg. set] T: 0.00ns= 0.000c 5407 APX_F :{EVEX} CCMPcc r8, r8, dfv L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5408 APX_F :{EVEX} CCMPcc r16, r16, dfv L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5409 APX_F :{EVEX} CCMPcc r32, r32, dfv L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5410 APX_F :{EVEX} CCMPcc r64, r64, dfv L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5411 APX_F :{EVEX} XOR r8, r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5412 APX_F :{EVEX} XOR r16, r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5413 APX_F :{EVEX} XOR r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5414 APX_F :{EVEX} XOR r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5415 APX_F :{EVEX} ANDN r32, r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5416 APX_F :{EVEX} ANDN r64, r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5417 APX_F :{EVEX} ROL r8, r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5418 APX_F :{EVEX} ROL r16, r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5419 APX_F :{EVEX} ROL r32, r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5420 APX_F :{EVEX} ROL r64, r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5421 APX_F :{EVEX} ROL r8, r8, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5422 APX_F :{EVEX} ROL r16, r16, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5423 APX_F :{EVEX} ROL r32, r32, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5424 APX_F :{EVEX} ROL r64, r64, 1 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5425 APX_F :{REX2} MOV r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5426 APX_F :{REX2} MOV r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5427 APX_F :{REX2} MOV r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5428 APX_F :{REX2} MOV r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5429 APX_F :{REX2} XOR r8, r8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5430 APX_F :{REX2} XOR r16, r16 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5431 APX_F :{REX2} XOR r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5432 APX_F :{REX2} XOR r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5433 APX_F :{REX2} MOV r8, [m8] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5434 APX_F :{REX2} MOV r16, [m16] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5435 APX_F :{REX2} MOV r32, [m32] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5436 APX_F :{REX2} MOV r64, [m64] L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5437 APX_F :{REX2} ROL r8, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5438 APX_F :{REX2} ROL r16, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5439 APX_F :{REX2} ROL r32, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5440 APX_F :{REX2} ROL r64, imm8 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5441 APX_F :{EVEX} MOVBE r32, r32 L: 0.00ns= 0.00c T: 0.00ns= 0.000c 5442 APX_F :{EVEX} MOVBE r64, r64 L: 0.00ns= 0.00c T: 0.00ns= 0.000c